Inventor
JAVIER REYNALDO CORPUZ
US9 patents
Patents
9 patentsUS9373569B1Jun 21, 2016
Flat no-lead packages with electroplated edges
TEXAS INSTRUMENTS INC4 citations82
US9768098B2Sep 19, 2017
Packaged semiconductor device having stacked attached chips overhanging the assembly pad
TEXAS INSTRUMENTS INC6 citations71
US11769247B2Sep 26, 2023
Exposed pad integrated circuit package
TEXAS INSTRUMENTS INC0 citations60
US11195269B2Dec 7, 2021
Exposed pad integrated circuit package
TEXAS INSTRUMENTS INC0 citations60
US9576886B1Feb 21, 2017
Flat no-lead packages with electroplated edges
TEXAS INSTRUMENTS INC1 citations60
US9219019B2Dec 22, 2015
Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound
TEXAS INSTRUMENTS INC3 citations60
US10580723B2Mar 3, 2020
Flat no-lead packages with electroplated edges
TEXAS INSTRUMENTS INC0 citations50
US10366947B2Jul 30, 2019
Flat no-lead packages with electroplated edges
TEXAS INSTRUMENTS INC0 citations50
US9721859B2Aug 1, 2017
Semi-hermetic semiconductor package
TEXAS INSTRUMENTS INC0 citations39