Inventor

KHATER MARWAN H

US107 patents

⚠️ This page may combine multiple inventors who share the name “KHATER MARWAN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHATER MARWAN H

IBM

Field plate in heterojunction bipolar transistor with improved break-down voltage

Multivalent oxide cap for analog switching resistive memory

Scaled cross bar array with undercut electrode

Silicon photonics alignment tolerant vertical grating couplers

Methods to improve the SiGe heterojunction bipolar device performance

Bipolar transistor with extrinsic stress layer

Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same

Structure and method of forming a bipolar transistor having a self-aligned raised extrinsic base using link-up region formed from an opening therein

Silicon photonics integration method and structure

Bipolar transistor with dual shallow trench isolation and low base resistance

Bipolar transistor structure with self-aligned raised extrinsic base and methods

Structure and method of forming bipolar transistor having a self-aligned raised extrinsic base using self-aligned etch stop layer

Bipolar transistor structure with self-aligned raised extrinsic base and methods

Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border

Method of base formation in a BiCMOS process

Structure and method for making heterojunction bipolar transistor having self-aligned silicon-germanium raised extrinsic base

Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance

Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes

Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes

Scaled cross bar array with undercut electrode

Silicon photonics integration method and structure

Bipolar junction transistors with reduced base-collector junction capacitance

Heterojunction bipolar transistors with an airgap between the extrinsic base and collector

Bipolar junction transistors with reduced base-collector junction capacitance

Heterojunction bipolar transistors with reduced parasitic capacitance

Material structures for front-end of the line integration of optical polarization splitters and rotators

Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region

Stress engineered multi-layers for integration of CMOS and Si nanophotonics

Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases

Method of fabricating self-aligned bipolar transistor having tapered collector

Methods to improve the SiGe heterojunction bipolar device performance

Structure and method of self-aligned bipolar transistor having tapered collector

Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same

Bipolar transistor with a very narrow emitter feature

Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same

GLOBALFOUNDRIES INC

Profile control over a collector of a bipolar junction transistor

Bipolar junction transistors with a buried dielectric region in the active device region

Trench isolation structures and methods for bipolar junction transistors

Photodetector methods and photodetector structures

NING TAK H

SOI SiGe-base lateral bipolar junction transistor

SOI SiGe-base lateral bipolar junction transistor

UNIV TEXAS

Transmission line based inductively coupled plasma source with stable impedance

High density plasma source for semiconductor processing

GLOBALFOUNDARIES INC

Heterojunction bipolar transistor with improved performance and breakdown voltage

FREESCALE SEMICONDUCTOR INC

FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer

APPLIED MATERIALS INC

Particle contamination cleaning from substrates using plasmas, reactive gases, and mechanical agitation

ASSEFA SOLOMON

Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration

CAMILLO-CASTILLO RENATA

Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases

DENNARD ROBERT H

Isolation structures for SOI devices with ultrathin SOI and ultrathin box

KHATER MARWAN H

SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics