Inventor

LUEKER-BODEN Martin

US42 patents

⚠️ This page may combine multiple inventors who share the name “LUEKER-BODEN Martin”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUEKER-BODEN Martin

SANDISK TECHNOLOGIES LLC

Vector-matrix multiplication using non-volatile memory cells

Configurable precision neural network with differential binary non-volatile memory cell structure

Dynamic resource management in circuit bound array architecture

Binary weighted voltage encoding scheme for supporting multi-bit input precision

Recurrent neural network inference engine with gated recurrent unit cell and non-volatile memory arrays

Scalable search system design with single level cell NAND-based binary and ternary valued content addressable memory cells

Realization of neural networks with ternary inputs and binary weights in NAND memory arrays

Differential non-volatile memory cell for artificial neural network

Cross-point memory array addressing

Dropout in neutral networks using threshold switching selectors in non-volatile memories

Multi-precision digital compute-in-memory deep neural network engine for flexible and energy efficient inferencing

Compute-in-memory deep neural network inference engine using low-rank approximation technique

Realization of neural networks with ternary inputs and ternary weights in NAND memory arrays

Accelerating sparse matrix multiplication in storage class memory-based convolutional neural network inference

Realization of binary neural networks in NAND memory arrays

Current reference circuit with process, voltage, and wide-range temperature compensation

Vertical mapping and computing for deep neural networks in non-volatile memory

Kernel transformation techniques to reduce power consumption of binary input, binary weight in-memory convolutional neural network inference engine

Vertical mapping and computing for deep neural networks in non-volatile memory

Crosspoint memory architecture for high bandwidth operation with small page buffer

Binary weighted voltage encoding scheme for supporting multi-bit input precision

ZQ calibration circuit and method for memory interfaces

Reconfigurable input precision in-memory computing

Low line-sensitivity and process-portable reference voltage generator circuit

WESTERN DIGITAL TECH INC

Hardware accelerated discretized neural network

Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning

Accelerating binary neural networks within latch structure of non-volatile memory devices

Super-sparse image compression using cross-bar non-volatile memory device

Non-volatile cross-bar memory with on-chip processing circuitry

Hardware accelerated discretized neural network

Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning

Disaggregation of control path and data path

Shifting architecture for data reuse in a neural network

Mesh network-on-a-chip (NOC) with heterogeneous routers

Memory controller support for mixed read

Memory controller with common request buffer

Data receiver design in DDR memory interfaces

Data storage device and method for hiding tweak generation latency

SANDISK TECHNOLOGIES INC

Bypass buffer for worn out codewords

Memory with write address delay circuit

Data storage device and method for hiding tweak generation latency

Supporting mixed read in non-volatile memory controller