P

Inventor

PETRARCA KEVIN SHAWN

US19 patents

Patents

19 patents
US7115997B2Oct 3, 2006

Seedless wirebond pad plating

IBM17 citations92
US6819000B2Nov 16, 2004

High density area array solder microjoining interconnect structure and fabrication method

IBM28 citations92
US6732908B2May 11, 2004

High density raised stud microjoining system and methods of fabricating the same

IBM19 citations92
US6661098B2Dec 9, 2003

High density area array solder microjoining interconnect structure and fabrication method

IBM18 citations92
US7943412B2May 17, 2011

Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters

IBM24 citations91
US6864578B2Mar 8, 2005

Internally reinforced bond pads

IBM16 citations89
US12444653B2Oct 14, 2025

Buried power rail at tight cell-to-cell space

IBM2 citations74
US6747472B2Jun 8, 2004

Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same

IBM8 citations72
US7273804B2Sep 25, 2007

Internally reinforced bond pads

IBM6 citations71
US7825019B2Nov 2, 2010

Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits

IBM4 citations63
US7534651B2May 19, 2009

Seedless wirebond pad plating

IBM3 citations63
US12033981B2Jul 9, 2024

Create a protected layer for interconnects and devices in a packaged quantum structure

IBM0 citations62
US7855137B2Dec 21, 2010

Method of making a sidewall-protected metallic pillar on a semiconductor substrate

IBM6 citations62
US7833893B2Nov 16, 2010

Method for forming conductive structures

IBM5 citations62
US6982493B2Jan 3, 2006

Wedgebond pads having a nonplanar surface structure

IBM2 citations62
US7541277B1Jun 2, 2009

Stress relaxation, selective nitride phase removal

IBM2 citations61
US6284574B1Sep 4, 2001

Method of producing heat dissipating structure for semiconductor devices

IBM4 citations60
US12406930B2Sep 2, 2025

Structure containing a via-to-buried power rail contact structure or a via-to-backside power rail contact structure

IBM0 citations51
US12178142B2Dec 24, 2024

Layered substrate structures with aligned optical access to electrical devices

IBM0 citations50