P

Inventor

GUO DECHAO

US234 patents
⚠️ This page may combine multiple inventors who share the name “GUO DECHAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

25 patents
US9318581B1Apr 19, 2016

Forming wrap-around silicide contact on finFET

IBM82 citations98
US11069684B1Jul 20, 2021

Stacked field effect transistors with reduced coupling effect

IBM49 citations95
US10797163B1Oct 6, 2020

Leakage control for gate-all-around field-effect transistor devices

IBM26 citations94
US9721848B1Aug 1, 2017

Cutting fins and gates in CMOS devices

IBM32 citations94
US9397197B1Jul 19, 2016

Forming wrap-around silicide contact on finFET

IBM28 citations94
US9773893B1Sep 26, 2017

Forming a sacrificial liner for dual channel devices

IBM11 citations93
US9704754B1Jul 11, 2017

Self-aligned spacer for cut-last transistor fabrication

IBM13 citations93
US8928086B2Jan 6, 2015

Strained finFET with an electrically isolated channel

IBM19 citations93
US9922984B1Mar 20, 2018

Threshold voltage modulation through channel length adjustment

IBM10 citations92
US9157887B2Oct 13, 2015

Graphene sensor

IBM19 citations92
US9960254B1May 1, 2018

Replacement metal gate scheme with self-alignment gate for vertical field effect transistors

IBM22 citations91
US11201153B2Dec 14, 2021

Stacked field effect transistor with wrap-around contacts

IBM9 citations86
US10510892B2Dec 17, 2019

Forming a sacrificial liner for dual channel devices

IBM3 citations84
US10096713B1Oct 9, 2018

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

IBM7 citations84
US9978750B1May 22, 2018

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

IBM11 citations84
US9922983B1Mar 20, 2018

Threshold voltage modulation through channel length adjustment

IBM10 citations84
US9412641B1Aug 9, 2016

FinFET having controlled dielectric region height

IBM10 citations84
US9390976B2Jul 12, 2016

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

IBM8 citations84
US9190520B2Nov 17, 2015

Strained finFET with an electrically isolated channel

IBM15 citations84
US9171954B2Oct 27, 2015

FinFET structure and method to adjust threshold voltage in a FinFET structure

IBM9 citations84
US8940595B2Jan 27, 2015

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

IBM8 citations84
US8853788B2Oct 7, 2014

Replacement gate electrode with planar work function material layers

IBM6 citations84
US8741700B1Jun 3, 2014

Non-volatile graphene nanomechanical switch

IBM8 citations84
US8735947B1May 27, 2014

Non-volatile graphene nanomechanical switch

IBM12 citations84
US8354313B2Jan 15, 2013

Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures

IBM8 citations84

GUO DECHAO

13 patents

CAI MING

6 patents

CAO QING

2 patents

YUAN JUN

1 patent

WONG KEITH KWONG HON

1 patent

FRANK MARTIN M

1 patent

BRYANT ANDRES

1 patent

Showing the top 50 of 234 patents by PatentIndex Score.