Inventor

YEH CHUN-CHEN

US371 patents

⚠️ This page may combine multiple inventors who share the name “YEH CHUN-CHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEH CHUN-CHEN

IBM

Inner spacer for nanosheet transistors

Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain

Fabrication of vertical field effect transistor structure with controlled gate length

Stacked nanowire field effect transistor

Stacked field effect transistors with reduced coupling effect

Nanosheet transistors having thin and thick gate dielectric material

Forming air-gap spacer for vertical field effect transistor

Vertical vacuum channel transistor

Forming vertical and horizontal field effect transistors on the same substrate

Forming strained and relaxed silicon and silicon germanium fins on the same wafer

Forming vertical transistors and metal-insulator-metal capacitors on the same chip

Self aligned epitaxial based punch through control

Nanowire semiconductor device including lateral-etch barrier region

Self-aligned contact process enabled by low temperature

Independent gate vertical FinFET structure

Dual epitaxial process including spacer adjustment

Strained silicon nFET and silicon germanium pFET on same wafer

Preventing Fin erosion and limiting EPI overburden in FinFET structures by composite hardmask

Preventing FIN erosion and limiting Epi overburden in FinFET structures by composite hardmask

finFET eDRAM strap connection structure

Stacked field effect transistor with wrap-around contacts

Nanosheet transistor having improved bottom isolation

Formation of VFET and finFET

Reduced source/drain coupling for CFET

Nanosheet transistor with dual inner airgap spacers

Nanosheet transistor with optimized junction and cladding defectivity control

VFET CMOS dual epitaxy integration

Vertical transistors with improved top source/drain junctions

Vertically stacked multi-channel transistor structure

Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor

Extended contact area using undercut silicide extensions

Nanosheet transistors on bulk material

Inner spacer for nanosheet transistors

ST MICROELECTRONICS INC

Multi-channel gate-all-around FET

Multi-channel gate-all-around FET

FinFETs having strained channels, and methods of fabricating finFETs having strained channels

Methods for forming vertical and sharp junctions in finFET structures

LDMOS FinFET device using a long channel region and method of manufacture

FinFETs and techniques for controlling source and drain junction profiles in finFETs

GLOBALFOUNDRIES INC

Stacked nanosheet field-effect transistor with air gap spacers

Method of forming vertical field effect transistors with different gate lengths and a resulting structure

Vertical transistor having buried contact, and contacts using work function metals and silicides

Air gap adjacent a bottom source/drain region of vertical transistor device

Methods of forming vertical transistor devices with different effective gate lengths

Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure

CAI MING

Fin field effect transistor with variable channel thickness for threshold voltage tuning

Integration of SMT in replacement gate FINFET process flow

Structure and method to form passive devices in ETSOI process flow

BASKER VEERARAGHAVAN S

SOI FinFET with recessed merged Fins and liner for enhanced stress coupling

Method for fabricating finFET with merged fins and vertical silicide