Inventor

MOENCH JERRY D

US34 patents

⚠️ This page may combine multiple inventors who share the name “MOENCH JERRY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOENCH JERRY D

ADVANCED MICRO DEVICES INC

Logic allocator for a programmable logic device

An I/O macrocell for a programmable logic device

Multiple array high performance programmable logic device family

Flexible, programmable cell array interconnected by a programmable switch matrix

High density programmable logic device

Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix

Interlaced layout configuration for differential pairs of interconnect lines

Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices

Method and apparatus for sensing a programming state of fuses

Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix

High speed centralized switch matrix for a programmable logic device

Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit

Memory array with global bitline domino read/write scheme

Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device

Microprocessor including bank-pipelined cache with asynchronous data blocks

Switch matrix multiplexers

Multi-ported register cell with randomly accessible history

MOTOROLA INC

ROM Storage location having more than two states

Partial memory selection using a programmable decoder

Serial data mode circuit for a memory

Digital predecoding system

Self latching buffer

Substrate bias voltage regulator

Substrate bias regulator

Substrate bias pump

Quiet row selection circuitry

Quiet column decoder

Differential capacitive buffer

Dynamic output buffer

Speed-up circuit

Schmitt trigger circuit

Static storage technique for four transistor IGFET memory cell

Signal generator having minimum delay

Write circuit for a read/write memory