Inventor

CHIA YONG POO

SG60 patents

⚠️ This page may combine multiple inventors who share the name “CHIA YONG POO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIA YONG POO

MICRON TECHNOLOGY INC

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Method of making multichip wafer level packages and computing systems incorporating same

Packaged image sensing microelectronic devices including a lead and methods of packaging image sensing microelectronic devices including a lead

Castellated chip-scale packages and methods for fabricating the same

Method of forming a conductive via through a wafer

Multi-chip wafer level system packages and methods of forming same

Multichip wafer level packages and computing systems incorporating same

Castellation wafer level packaging of integrated circuit chips

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Interconnects for packaged semiconductor devices and methods for manufacturing such devices

Semiconductor assemblies and methods of manufacturing such assemblies including forming trenches in a first side of the molding material

Semiconductor device assemblies and packages with edge contacts and sacrificial substrates and other intermediate structures used or formed in fabricating the assemblies or packages

Wafer level packaging

Method for packaging circuits and packaged circuits

Super high density module with integrated wafer level packages

Super high density module with integrated wafer level packages

Leadless packaging for image sensor devices

Leadless packaging for image sensor devices and methods of assembly

Multichip wafer level packages and computing systems incorporating same

Multiple chip semiconductor package and method of fabricating same

Multiple chip semiconductor package

Multiple chip semiconductor package

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

Super high density module with integrated wafer level packages

Semiconductor assemblies and methods of manufacturing such assemblies including trenches in a molding material between semiconductor die

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Semiconductor dies with recesses, associated leadframes, and associated systems and methods

Castellation wafer level packaging of integrated circuit chips

Methods and apparatus for testing and burn-in of semiconductor devices

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

Multiple chip semiconductor package

Castellation wafer level packaging of integrated circuit chips

CHIA YONG POO

Method for packaging circuits

Method for packaging circuits

Super high-density module with integrated wafer level packages

BOON SUAN JEUNG

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Semiconductor device assemblies and packages

Packaged semiconductor assemblies and methods for manufacturing such assemblies

CHUA SWEE KWANG

Wafer level packaging

Wafer level packaging

JIANG TONGBI

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

ENG MEOW KOON

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

LODESTAR LICENSING GROUP LLC

Packaged integrated circuit devices with through-body conductive vias, and methods of making same

APTINA IMAGING CORP

Microelectronic imagers and methods for manufacturing such microelectronic imagers