Inventor
SELISKAR JOHN J
US13 patents
⚠️ This page may combine multiple inventors who share the name “SELISKAR JOHN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
6 patentsUS5985705ANov 16, 1999
Low threshold voltage MOS transistor and method of manufacture
LSI LOGIC CORP148 citations98
US6355532B1Mar 12, 2002
Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET
LSI LOGIC CORP118 citations96
US6316817B1Nov 13, 2001
MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor
LSI LOGIC CORP46 citations96
US6115233ASep 5, 2000
Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region
LSI LOGIC CORP78 citations96
US6525377B1Feb 25, 2003
Low threshold voltage MOS transistor and method of manufacture
LSI LOGIC CORP22 citations92
US6284586B1Sep 4, 2001
Integrated circuit device and method of making the same using chemical mechanical polishing to remove material in two layers following masking
LSI LOGIC CORP29 citations92
SELISKAR JOHN J
5 patentsUS7211864B2May 1, 2007
Fully-depleted castellated gate MOSFET device and method of manufacture thereof
SELISKAR JOHN J136 citations97
US7968409B2Jun 28, 2011
Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof
SELISKAR JOHN J20 citations92
US7714384B2May 11, 2010
Castellated gate MOSFET device capable of fully-depleted operation
SELISKAR JOHN J37 citations92
US7719058B2May 18, 2010
Mixed-signal semiconductor platform incorporating fully-depleted castellated-gate MOSFET device and method of manufacture thereof
SELISKAR JOHN J13 citations83
US7439139B2Oct 21, 2008
Fully-depleted castellated gate MOSFET device and method of manufacture thereof
SELISKAR JOHN J13 citations83
SYMBIOS INC
2 patentsUS5858828AJan 12, 1999
Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor
SYMBIOS INC48 citations96
US5780329AJul 14, 1998
Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask
SYMBIOS INC8 citations73