Inventor

MOUDGILL MAYAN

US62 patents

⚠️ This page may combine multiple inventors who share the name “MOUDGILL MAYAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOUDGILL MAYAN

OPTIMUM SEMICONDUCTOR TECH INC

Vector processor configured to operate on variable length vectors using digital signal processing instructions

Vector processor configured to operate on variable length vectors using implicitly typed instructions

Vector processor configured to operate on variable length vectors using instructions to combine and split vectors

Computer processor that implements pre-translation of virtual addresses

System and method to implement masked vector instructions

Processor with mode support

Monolithic vector processor configured to operate on variable length vectors using a vector length register

Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions

Vector processor configured to operate on variable length vectors with asymmetric multi-threading

Computer processor that implements pre-translation of virtual addresses with target registers

System and architecture including processor and neural network accelerator

System and architecture of neural network accelerator

Vector processor to operate on variable length vectors using graphics processing instructions

Computer processor with register direct branches and employing an instruction preload structure

Variable translation-lookaside buffer (TLB) indexing

Device and method for hardware-efficient adaptive calculation of floating-point trigonometric functions using coordinate rotate digital computer (CORDIC)

Device and method for calculating elementary functions using successive cumulative rotation circuit

Vector processor to operate on variable length vectors with out-of-order execution

Vector processor configured to operate on variable length vectors using instructions that change element widths

SANDBRIDGE TECHNOLOGIES INC

Inter-thread communications using shared interrupt register

Method and apparatus for token triggered multithreading

Processor having parallel vector multiply and reduce operations with sequential semantics

Multi-threaded processor having compound instruction and operation formats

Method and apparatus for multithreaded cache with cache eviction based on thread identifier

Multithreaded processor with efficient processing for convergence device applications

Method and apparatus for thread-based memory access in a multithreaded processor

Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy

Method and apparatus for register file port reduction in a multithreaded processor

Rake receiver with multi-path interference accommodation

Fast transmitter based on table lookup

Doppler compensated receiver

Method for recognition of full-word saturating addition and subtraction

IBM

Method for preventing buffer overflow attacks

Vector register file with arbitrary vector addressing

Processor with compiler-allocated, variable length intermediate storage

Method and apparatus for reordering memory operations in a processor

Vector register file with arbitrary vector addressing

System and method for refreshing memory devices

System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form

Digital signal processor with cascaded SIMD organization

Microprocessor including register renaming unit for renaming target registers in an instruction with physical registers in a register sub-file

Method of renaming registers in register file and microprocessor thereof

Method and apparatus for reducing encoding needs and ports to shared resources in a processor

Ultra low power adder with sum synchronization

HOKENEK ERDEM

Multithreaded processor with multiple concurrent pipelines per thread

Multithreaded processor with multiple concurrent pipelines per thread

Multithreaded processor with multiple concurrent pipelines per thread

CORNELL RES FOUNDATION INC

Multiple issue static speculative instruction scheduling with path tag and precise interrupt handling

MOUDGILL MAYAN

Implementation of arbitrary galois field arithmetic on a programmable processor

WANG SHENGHONG

Power saving circuit using a clock buffer and multiple flip-flops