Inventor

GLOSSNER C JOHN

US41 patents

⚠️ This page may combine multiple inventors who share the name “GLOSSNER C JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GLOSSNER C JOHN

OPTIMUM SEMICONDUCTOR TECH INC

Vector processor configured to operate on variable length vectors using digital signal processing instructions

Vector processor configured to operate on variable length vectors using implicitly typed instructions

Vector processor configured to operate on variable length vectors using instructions to combine and split vectors

Computer processor that implements pre-translation of virtual addresses

Processor with mode support

Monolithic vector processor configured to operate on variable length vectors using a vector length register

Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions

Vector processor configured to operate on variable length vectors with asymmetric multi-threading

Computer processor that implements pre-translation of virtual addresses with target registers

Method and apparatus for enabling a processor to generate pipeline control signals

Multithreading using an ordered list of hardware contexts

Vector processor to operate on variable length vectors using graphics processing instructions

Computer processor with register direct branches and employing an instruction preload structure

Vector processor to operate on variable length vectors with out-of-order execution

Computer processor with address register file

Opportunity multithreading in a multithreaded processor with instruction chaining capability

SANDBRIDGE TECHNOLOGIES INC

Method and apparatus for token triggered multithreading

Processor having parallel vector multiply and reduce operations with sequential semantics

Multi-threaded processor having compound instruction and operation formats

Method and apparatus for multithreaded cache with cache eviction based on thread identifier

Multithreaded processor with efficient processing for convergence device applications

Method and apparatus for thread-based memory access in a multithreaded processor

Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy

Method and apparatus for register file port reduction in a multithreaded processor

Arithmetic unit for addition or subtraction with preliminary saturation detection

Processor reduction unit for accumulation of multiple operands with or without saturation

Convergence device with dynamic program throttling that replaces noncritical programs with alternate capacity programs based on power indicator

Arithmetic circuit with balanced logic levels for low-power operation

HOKENEK ERDEM

Multithreaded processor with multiple concurrent pipelines per thread

Multithreaded processor with multiple concurrent pipelines per thread

Multithreaded processor with multiple concurrent pipelines per thread

Multithreaded processor with multiple concurrent pipelines per thread

Multithreaded processor with multiple concurrent pipelines per thread

AGERE SYST GUARDIAN CORP

Virtual single-cycle execution in pipelined processors

Cooperative interconnection for reducing port pressure in clustered microprocessors

Shared datapath processor utilizing stack-based and register-based storage spaces

File replication methods and apparatus for reducing port pressure in a clustered processor

Duplicator interconnection methods and apparatus for reducing port pressure in a clustered processor

LUCENT TECHNOLOGIES INC

Compiler-controlled dynamic instruction dispatch in pipelined processors

Multiple machine view execution in a computer system

AGERE SYSTEMS INC

Method and apparatus for reducing power consumption in a pipelined processor