Inventor
LEVENSTEIN SHELDON B
US30 patents
⚠️ This page may combine multiple inventors who share the name “LEVENSTEIN SHELDON B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
28 patentsUS6088788AJul 11, 2000
Background completion of instruction and associated fetch request in a multithread processor
IBM123 citations95
US7228385B2Jun 5, 2007
Processor, data processing system and method for synchronizing access to data in shared memory
IBM39 citations93
US7200717B2Apr 3, 2007
Processor, data processing system and method for synchronizing access to data in shared memory
IBM20 citations93
US7350051B2Mar 25, 2008
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
IBM15 citations92
US5586331ADec 17, 1996
Duplicated logic and interconnection system for arbitration among multiple information processors
IBM39 citations92
US5751990AMay 12, 1998
Abridged virtual address cache directory
IBM48 citations91
US5206941AApr 27, 1993
Fast store-through cache memory
IBM23 citations91
US5131085AJul 14, 1992
High performance shared main storage interface
IBM44 citations91
US7318127B2Jan 8, 2008
Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor
IBM17 citations84
US7284094B2Oct 16, 2007
Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class
IBM14 citations84
US5463741AOct 31, 1995
Duplicated logic and interconnection system for arbitration among multiple information processors
IBM15 citations82
US7809924B2Oct 5, 2010
System for generating effective address
IBM15 citations81
US5566305AOct 15, 1996
Duplicated logic and interconnection system for arbitration among multiple information processors
IBM9 citations74
US10078514B2Sep 18, 2018
Techniques for dynamic sequential instruction prefetching
IBM4 citations73
US7380062B2May 27, 2008
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
IBM5 citations73
US7360058B2Apr 15, 2008
System and method for generating effective address
IBM6 citations71
US7092270B2Aug 15, 2006
Apparatus and method for detecting multiple hits in CAM arrays
IBM8 citations71
US7571283B2Aug 4, 2009
Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
IBM7 citations70
US5339397AAug 16, 1994
Hardware primary directory lock
IBM19 citations69
US7962722B2Jun 14, 2011
Branch target address cache with hashed indices
IBM2 citations63
US7197604B2Mar 27, 2007
Processor, data processing system and method for synchronzing access to data in shared memory
IBM6 citations63
US10379857B2Aug 13, 2019
Dynamic sequential instruction prefetching
IBM1 citations62
US7603543B2Oct 13, 2009
Method, apparatus and program product for enhancing performance of an in-order processor with long stalls
IBM2 citations62
US7831775B2Nov 9, 2010
System and method for tracking changes in L1 data cache directory
IBM0 citations52
US7401186B2Jul 15, 2008
System and method for tracking changes in L1 data cache directory
IBM0 citations52
US7788450B2Aug 31, 2010
Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
IBM0 citations51
US7660965B2Feb 9, 2010
Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
IBM1 citations51
US7302525B2Nov 27, 2007
Method and apparatus for efficiently accessing both aligned and unaligned data from a memory
IBM0 citations51