Inventor

PAN SHANJEN

US19 patents

⚠️ This page may combine multiple inventors who share the name “PAN SHANJEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN SHANJEN

TEXAS INSTRUMENTS INC

Drain extended MOS devices with self-aligned floating region and fabrication methods therefor

Method for manufacturing a MOS transistor having reduced 1/f noise

Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof

Drain extended PMOS transistor with increased breakdown voltage

Depletion drain-extended MOS transistors and methods for making the same

Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof

Methods of fabricating high voltage devices

Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices

Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices

Methods for fabricating low CHC degradation mosfet transistors

Reduction of channel hot carrier effects in transistor devices

Reduction of channel hot carrier effects in transistor devices

Electrically erasable programmable non-volatile memory

CIRRUS LOGIC INT SEMICONDUCTOR LTD

Dual device semiconductor structures with shared drain

Dual device semiconductor structures with shared drain

Pinched doped well for a junction field effect transistor (JFET) isolated from the substrate

CIRRUS LOGIC INC

Fully depleted region for reduced parasitic capacitance between a poly-silicon layer and a substrate region

Formation of electrical components on a semiconductor substrate by polishing to isolate the components

PAN SHANJEN

N-channel erasable programmable non-volatile memory