Inventor

MEANEY PATRICK J

US118 patents

⚠️ This page may combine multiple inventors who share the name “MEANEY PATRICK J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEANEY PATRICK J

IBM

Heterogeneous recovery in a redundant memory system

First-in-first-out queue-based command spreading

Detecting address faults in an ECC-protected memory

Resource arbitration system with resource checking and lockout avoidance

Method to determine retries for parallel ECC correction in a pipeline

Method and apparatus for collecting failure information on error correction code (ECC) protected data

Generating special uncorrectable error codes for failure isolation

Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing

Programmable clock tuning system and method

Method for tagging uncorrectable errors for symmetric multiprocessors

Error correction potency improvement via added burst beats in a dram access cycle

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

High efficiency redundant array of independent memory

Reestablishing synchronization in a memory system

Synchronization and order detection in a memory system

Address mapping including generic bits for universal addressing independent of memory type

Bad wordline/array detection in memory

Collecting failure information on error correction code (ECC) protected data

User-controlled targeted cache purge

Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code

Single symbol correction double symbol detection code employing a modular H-matrix

Method system and program products for error correction code conversion

Dual asynchronous and synchronous memory system

Dual asynchronous and synchronous memory system

Double data rate chaining for synchronous DDR interfaces

System resource enable apparatus with wake-up feature

System resource conflict resolution apparatus

Method of correcting single errors

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Power-reduced redundant array of independent memory (RAIM) system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Reducing uncorrectable errors based on a history of correctable errors

Predictive scheduler for memory rank switching

Partial data replay in a distributed memory buffer system

Reducing uncorrectable errors based on a history of correctable errors

Synchronization and order detection in a memory system

Error injection and error counting during memory scrubbing operations

Error injection and error counting during memory scrubbing operations

Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements

Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface

Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface

ALVES LUIZ C

Correcting memory device and memory channel failures in the presence of known memory device failures

Error correction and detection in a redundant memory system

RAIM system using decoding of virtual ECC

MEANEY PATRICK J

Method, system and computer program product for processing error information in a system

Bad wordline/array detection in memory

Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems

LASTRAS-MONTANO LUIS A

Failing bus lane detection using syndrome analysis

GOWER KEVIN C

Heterogeneous recovery in a redundant memory system

BAIR DEAN G

Hierarchical error injection for complex RAIM/ECC design