Inventor

PERLMUTTER URI

IL67 patents

⚠️ This page may combine multiple inventors who share the name “PERLMUTTER URI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PERLMUTTER URI

APPLE INC

Adaptive estimation of memory cell read thresholds

Efficient readout from memory cells using data compression

Redundant data storage schemes for multi-die memory systems

Memory device with internal signal processing unit

Memory device with internal signal processing unit

Redundant data storage schemes for multi-die memory systems

Adaptive estimation of memory cell read thresholds

Redundant data storage schemes for multi-die memory systems

Efficient readout from memory cells using data compression

Redundant data storage schemes for multi-die memory systems

Efficient re-read operations in analog memory cell arrays

Storage at M bits/cell density in N bits/cell analog memory cell devices, M&gt;N

SOMMER NAFTALI

Database of memory read thresholds

Data scrambling schemes for memory devices

Efficient readout schemes for analog memory cell devices using multiple read threshold sets

Data scrambling in memory devices

Selective re-programming of analog memory cells

Selective re-programming of analog memory cells

Data scrambling schemes for memory devices

Efficient readout schemes for analog memory cell devices

SHALVI OFIR

Redundant data storage schemes for multi-die memory systems

Redundant data storage in multi-die memory systems

Reliable data storage in analog memory cells subjected to long retention periods

Storage at M bits/cell density in N bits/cell analog memory cell devices, M&gt;N

Programming orders for reducing distortion in arrays of multi-level analog memory cells

Segmented data storage

Programming orders for reducing distortion based on neighboring rows

Reducing distortion using joint storage

PERLMUTTER URI

Efficient readout from analog memory cells using data compression

Efficient re-read operations from memory devices

Memory device with multiple-accuracy read commands

Estimation of memory cell read thresholds by sampling inside programming level distribution intervals

Efficient interference cancellation in analog memory cell arrays

Efficient re-read operations in analog memory cell arrays

Efficient readout from analog memory cells using data compression

ANOBIT TECHNOLOGIES LTD

Estimation of memory cell read thresholds by sampling inside programming level distribution intervals

Programming analog memory cells for reduced variance after retention

Programming of analog memory cells using a single programming pulse per state transition

SOKOLOV DOTAN

Selective activation of programming schemes in analog memory cell arrays

Memory device with internal signap processing unit

Selective activation of programming schemes in analog memory cell arrays

INTEL IP CORP

Discrete levels envelope tracking

Transmit power control for uplink transmissions

Apparatuses and methods for compensating phase fluctuations

INTEL CORP

Resource unit (RU) allocation for EHT for power spectral density limitations

Preamble detection using frequency based correlation

OFDM signal acquisition

ANHOLT MICHA

Dual ECC decoder

SHACHAR MICHAEL

Memory system including a controller and processors associated with memory devices

GUREVITZ ASSAF

Method and apparatus for frame control header decoding using cyclic shifting of bits

Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N

Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N