Inventor

WILLIAMS KELLY L

US43 patents

⚠️ This page may combine multiple inventors who share the name “WILLIAMS KELLY L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WILLIAMS KELLY L

IBM

3-D single gate inverter

Precision IC resistor fabrication

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Method of implementing buried FET below and beside FinFET on bulk substrate

Semiconductor chip with power gating through silicon vias

Capacitor backup for SRAM

Semiconductor chip with power gating through silicon vias

Implementing semiconductor soc with metal via gate node high performance stacked transistors

Multiple-patterned semiconductor device channels

Multiple-patterned semiconductor device channels

Semiconductor device channels

Semiconductor device channels

Semiconductor device channels

Semiconductor device channels

Implementing buried FET below and beside FinFET on bulk substrate

Implementing vertical signal repeater transistors utilizing wire vias as gate nodes

Implementing hacking detection and block function at indeterminate times with priorities and limits

Side gate assist in metal gate first process

Interdigitated finFETs

Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone

ERICKSON KARL R

eDRAM having dynamic retention and performance tradeoff

FinFET with body contact

Independently voltage controlled volume of silicon on a silicon on insulator chip

Vertically stacked FETs with series bipolar junction transistor

Implementing semiconductor SoC with metal via gate node high performance stacked transistors

Plural differential pair employing FinFET structure

Implementing temporary disable function of protected circuitry by modulating threshold voltage of timing sensitive circuit

Deep trench embedded gate transistor

Enhanced thin film field effect transistor integration into back end of line

Implementing vertical signal repeater transistors utilizing wire vias as gate nodes

Utilizing gate phases for circuit tuning

Implementing eFuse circuit with enhanced eFuse blow operation

EQUISTAR CHEM LP

Polyethylene blends and films

Preparation of machine direction oriented polyethylene films

Polyolefin compositions

Preparation of multilayer polyethylene thin films

GLOBALFOUNDRIES INC

Implementing eDRAM stacked FET structure

Implementing buried FET utilizing drain of finFET as gate of buried FET

ERICKSON KARL ROBERT

Implementing eDRAM stacked FET structure

PAONE PHIL C

Soft error detection

PAONE PHIL CHRISTOPHER FELICE

Method for creating 3-D single gate inverter

ERICKSON KARL L

Implementing gate within a gate utilizing replacement metal gate process