P

Inventor

DELACRUZ JAVIER

US28 patents
⚠️ This page may combine multiple inventors who share the name “DELACRUZ JAVIER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XCELSIS CORP

19 patents
US10950547B2Mar 16, 2021

Stacked IC structure with system level wiring on multiple sides of the IC die

XCELSIS CORP145 citations99
US10886177B2Jan 5, 2021

3D chip with shared clock distribution network

XCELSIS CORP148 citations99
US10719762B2Jul 21, 2020

Three dimensional chip structure implementing machine trained network

XCELSIS CORP20 citations94
US10672744B2Jun 2, 2020

3D compute circuit with high density Z-axis interconnects

XCELSIS CORP27 citations94
US10672743B2Jun 2, 2020

3D Compute circuit with high density z-axis interconnects

XCELSIS CORP23 citations94
US10672663B2Jun 2, 2020

3D chip sharing power circuit

XCELSIS CORP25 citations94
US10672745B2Jun 2, 2020

3D processor

XCELSIS CORP25 citations94
US10607136B2Mar 31, 2020

Time borrowing between layers of a three dimensional chip stack

XCELSIS CORP21 citations94
US10600780B2Mar 24, 2020

3D chip sharing data bus circuit

XCELSIS CORP21 citations94
US10600735B2Mar 24, 2020

3D chip sharing data bus

XCELSIS CORP21 citations94
US10600691B2Mar 24, 2020

3D chip sharing power interconnect layer

XCELSIS CORP24 citations94
US10593667B2Mar 17, 2020

3D chip with shielded clock lines

XCELSIS CORP22 citations94
US10586786B2Mar 10, 2020

3D chip sharing clock interconnect layer

XCELSIS CORP22 citations94
US10580735B2Mar 3, 2020

Stacked IC structure with system level wiring on multiple sides of the IC die

XCELSIS CORP21 citations94
US10580757B2Mar 3, 2020

Face-to-face mounted IC dies with orthogonal top interconnect layers

XCELSIS CORP25 citations93
US11152336B2Oct 19, 2021

3D processor having stacked integrated circuit die

XCELSIS CORP4 citations73
US10978348B2Apr 13, 2021

3D chip sharing power interconnect layer

XCELSIS CORP2 citations73
US10970627B2Apr 6, 2021

Time borrowing between layers of a three dimensional chip stack

XCELSIS CORP0 citations62
US10892252B2Jan 12, 2021

Face-to-face mounted IC dies with orthogonal top interconnect layers

XCELSIS CORP0 citations62

ESILICON CORP

6 patents

ADEIA SEMICONDUCTOR INC

2 patents

INVENSAS BONDING TECH INC

1 patent