Inventor

SAVAGAONKAR UDAY R

US58 patents

⚠️ This page may combine multiple inventors who share the name “SAVAGAONKAR UDAY R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAVAGAONKAR UDAY R

INTEL CORP

Entry/exit architecture for protected device modules

Encryption interface

Using authenticated manifests to enable external certification of multi-processor platforms

Memory management in secure enclaves

Restricted component access to application memory

Control transfer termination instructions of an instruction set architecture (ISA)

Supporting secure memory intent

Technique for supporting multiple secure enclaves

Supporting secure memory intent

Secure memory repartitioning

Control transfer termination instructions of an instruction set architecture (ISA)

Paging in secure enclaves

Secure rendering of display surfaces

Method and apparatus for key provisioning of hardware devices

Dynamic generation of integrity manifest for run-time verification of software program

Identifier associated with memory locations for managing memory accesses

Supporting secure memory intent

Memory management in secure enclaves

Platform attestation and registration for servers

Platform attestation and registration for servers

Method and apparatus to provide secure application execution

Secure environment for graphics processing units

Memory encryption engine integration

Entry/exit architecture for protected device modules

Supporting secure memory intent

Supporting secure memory intent

Encryption interface

Method and apparatus to provide secure application execution

Instructions and logic to provide advanced paging capabilities for secure enclave page caches

Device and method for secure user interface gesture processing using processor graphics

Apparatus and method for page walk extension for enhanced security checks

Digital rights management (DRM) locker

Dynamic overdrive compensation test system and method

Encryption interface

Memory management in secure enclaves

Secure rendering of display surfaces

Techniques for enforcing a depth order policy for graphics in a display scene

Memory management in secure enclaves

CHHABRA SIDDHARTHA

Parallelized counter tree walk for low overhead memory replay protection

Secure video ouput path

Low-overhead cryptographic method and apparatus for providing memory confidentiality, integrity and replay protection

Memory encryption engine integration

MCKEEN FRANCIS X

Method and apparatus to provide secure application execution

Logging in secure enclaves

JOHNSON SIMON P

Technique for supporting multiple secure enclaves

DURHAM DAVID M

Method and apparatus for run-time in-memory patching of code from a service processor

SAHITA RAVI L

Software copy protection via protected execution of applications

SAVAGAONKAR UDAY R

Seamlessly encrypting memory regions to protect against hardware-based attacks

NARENDRA TRIVEDI ALPA T

Method and system for protecting memory information in a platform

ROZAS CARLOS V

Instructions and logic to provide advanced paging capabilities for secure enclave page caches