Inventor

LIU CHWEN-MING

TW34 patents

⚠️ This page may combine multiple inventors who share the name “LIU CHWEN-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU CHWEN-MING

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device with enhanced thermal dissipation and method for making the same

Semiconductor device having probe pads and seal ring

Semiconductor package structure and method for forming the same

Method of testing semiconductor package

Method for manufacturing semiconductor and structure thereof

Integrated circuit package structure and testing method using the same

Method of testing semiconductor package

Semiconductor device with enhanced thermal dissipation and method for making the same

Semiconductor package and method for making the same

Dual micro-electro mechanical system and manufacturing method thereof

Semiconductor package

Semiconductor device and manufacturing method of the same

Semiconductor package and method for making the same

Semiconductor package

Dual micro-electro mechanical system and manufacturing method thereof

Semiconductor package and method for manufacturing the same

Inductive device

Method for detecting defects in semiconductor device

Inductive device

Semiconductor package structure and method for manufacturing the same

Method for manufacturing semiconductor and structure thereof

Method of detecting delamination in an integrated circuit package structure

TAIWAN SEMICONDUCTOR MFG

Integrated defect yield management and query system

Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scanning electron microscopy by the utilization of specially designed test structures

Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scanning electron microscopy by the utilization of specially designed test structures

Method of making tapered poly profile for TFT device manufacturing

Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit

ARC layer enhancement for reducing metal loss during via etch

Method of making a variable resistance polysilicon conductor for an SRAM device

Procedure for eliminating bubbles formed during reflow of a dielectric layer over an LDD structure

Method for a MOS device manufacturing

Method for forming a dram stacked capacitor of zig-zag configuration

Effective load length increase by topography

TAIWAN SEMICONDUCTOR MFG COMPANY LTD

Dual micro-electro mechanical system and manufacturing method thereof