Inventor

HEO NAK-WON

KR15 patents

⚠️ This page may combine multiple inventors who share the name “HEO NAK-WON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAMSUNG ELECTRONICS CO LTD

12 patents

US6621315B2Sep 16, 2003

Delay locked loop circuit and method having adjustable locking resolution

SAMSUNG ELECTRONICS CO LTD89 citations97

US6940321B2Sep 6, 2005

Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device

SAMSUNG ELECTRONICS CO LTD28 citations92

US6717448B2Apr 6, 2004

Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device

SAMSUNG ELECTRONICS CO LTD15 citations82

US7551495B2Jun 23, 2009

Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof

SAMSUNG ELECTRONICS CO LTD4 citations62

US7518898B2Apr 14, 2009

Semiconductor memory device with strengthened power and method of strengthening power of the same

SAMSUNG ELECTRONICS CO LTD2 citations60

US7558127B2Jul 7, 2009

Data output circuit and method in DDR synchronous semiconductor device

SAMSUNG ELECTRONICS CO LTD0 citations52

US9858981B2Jan 2, 2018

Semiconductor memory devices including redundancy memory cells

SAMSUNG ELECTRONICS CO LTD0 citations51

US9524770B2Dec 20, 2016

Semiconductor memory devices including redundancy memory cells

SAMSUNG ELECTRONICS CO LTD0 citations51

HEO NAK-WON

2 patents

US8199588B2Jun 12, 2012

Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof

HEO NAK-WON5 citations70

US8625364B2Jan 7, 2014

Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode

HEO NAK-WON0 citations48

LEE YUN-YOUNG

1 patent

US9336906B2May 10, 2016

Semiconductor memory devices including redundancy memory cells

LEE YUN-YOUNG4 citations70

HEO NAK-WON

SAMSUNG ELECTRONICS CO LTD

Delay locked loop circuit and method having adjustable locking resolution

Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device

Data output method and data output circuit for applying reduced precharge level

Semiconductor memory device and method of supplying wordline voltage thereof

Data output circuit and method in DDR synchronous semiconductor device

Information processing system with memory modules of a serial bus architecture

Delay locked loop capable of compensating for delay of internal clock signal by variation of driving strength of output driver in semiconductor memory device

Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof

Semiconductor memory device with strengthened power and method of strengthening power of the same

Data output circuit and method in DDR synchronous semiconductor device

Semiconductor memory devices including redundancy memory cells

Semiconductor memory devices including redundancy memory cells

HEO NAK-WON

Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof

Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode

LEE YUN-YOUNG

Semiconductor memory devices including redundancy memory cells