Inventor
NOSOWICZ EUGENE JAMES
US5 patents
Patents
5 patentsUS7425855B2Sep 16, 2008
Set/reset latch with minimum single event upset
IBM8 citations70
US7103857B2Sep 5, 2006
Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices
IBM8 citations69
US7259602B2Aug 21, 2007
Method and apparatus for implementing fault tolerant phase locked loop (PLL)
IBM2 citations58
US7486123B2Feb 3, 2009
Set/reset latch with minimum single event upset
IBM1 citations48
US6954086B2Oct 11, 2005
Low power data storage element with enhanced noise margin
IBM0 citations48