Inventor
DEVGAN ANIRUDH
US29 patents
⚠️ This page may combine multiple inventors who share the name “DEVGAN ANIRUDH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS6347393B1Feb 12, 2002
Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation
IBM230 citations99
US6117182ASep 12, 2000
Optimum buffer placement for noise avoidance
IBM229 citations99
US7376001B2May 20, 2008
Row circuit ring oscillator method for evaluating memory cell performance
IBM81 citations98
US7301835B2Nov 27, 2007
Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
IBM67 citations98
US6842714B1Jan 11, 2005
Method for determining the leakage power for an integrated circuit
IBM82 citations98
US7483322B2Jan 27, 2009
Ring oscillator row circuit for evaluating memory cell performance
IBM17 citations92
US7137080B2Nov 14, 2006
Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit
IBM42 citations92
US7000205B2Feb 14, 2006
Method, apparatus, and program for block-based static timing analysis with uncertainty
IBM40 citations92
US6044209AMar 28, 2000
Method and system for segmenting wires prior to buffer insertion
IBM33 citations92
US6029117AFeb 22, 2000
coupled noise estimation method for on-chip interconnects
IBM50 citations92
US6662149B1Dec 9, 2003
Method and apparatus for efficient computation of moments in interconnect circuits
IBM44 citations89
US6308304B1Oct 23, 2001
Method and apparatus for realizable interconnect reduction for on-chip RC circuits
IBM38 citations89
US8001493B2Aug 16, 2011
Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions
IBM7 citations84
US7304895B2Dec 4, 2007
Bitline variable methods and circuits for evaluating static memory cell dynamic stability
IBM16 citations84
US7036104B1Apr 25, 2006
Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes
IBM15 citations79
US7561483B2Jul 14, 2009
Internally asymmetric method for evaluating static memory cell dynamic stability
IBM5 citations74
US6434729B1Aug 13, 2002
Two moment RC delay metric for performance optimization
IBM12 citations73
US7558136B2Jul 7, 2009
Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
IBM2 citations63
US7515491B2Apr 7, 2009
Method for evaluating leakage effects on static memory cell access time
IBM2 citations63
US6950996B2Sep 27, 2005
Interconnect delay and slew metrics based on the lognormal distribution
IBM3 citations63
US6868533B2Mar 15, 2005
Method and system for extending delay and slew metrics to ramp inputs
IBM3 citations63
US7827514B2Nov 2, 2010
Efficient electromagnetic modeling of irregular metal planes
IBM2 citations61
US7302661B2Nov 27, 2007
Efficient electromagnetic modeling of irregular metal planes
IBM4 citations61
US7134103B2Nov 7, 2006
Method, system, and product for verifying voltage drop across an entire integrated circuit package
IBM2 citations58
US6968306B1Nov 22, 2005
Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
IBM1 citations52