Inventor

SCHAEFER ANDRE

DE54 patents

⚠️ This page may combine multiple inventors who share the name “SCHAEFER ANDRE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHAEFER ANDRE

INFINEON TECHNOLOGIES AG

Method and device for transmission of adjustment information for data interface drivers for a RAM module

Input circuit for receiving a signal at an input on an integrated circuit

Memory device

Method for masking DQ bits

Semi-conductor component with clock relaying device

Logic signal level converter circuit and memory data output buffer using the same

Driver circuit for binary signals

Method for setting a termination voltage and an input circuit

Voltage supply for semiconductor memory

Differental current source for generating DRAM refresh signal

Memory device and method of accessing a memory device

Wafer handling device

Method of transferring signals between a memory device and a memory controller

Device in a memory circuit for definition of waiting times

Integrated circuit

Integrated circuit for receiving a clock signal, particularly for a semiconductor memory circuit

Method and input circuit for evaluating a data signal at an input of a memory component

Circuit configuration with protection device

Integrated circuit having an input circuit

Circuit device with clock pulse detection facility

Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement

INTEL CORP

Fast data eye retraining for a memory

Integrated voltage regulators with magnetically enhanced inductors

Techniques for accessing a dynamic random access memory array

Through-body-via isolated coaxial capacitor and techniques for forming same

Power management in multi-die assemblies

Power management in multi-die assemblies

Interlayer communications for 3D integrated circuit stack

Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems

Configuration for power reduction in DRAM

System and method for accessing memory

Stacked memory with interface providing offset interconnects

Resonant clocking for three-dimensional stacked devices

Techniques for accessing a dynamic random access memory array

SCHAEFER ANDRE

Adaptive address mapping with dynamic runtime memory mapping selection

Configuration for power reduction in DRAM

Separate microchannel voltage domains in stacked memory architecture

Adaptive address mapping with dynamic runtime memory mapping selection

Printing unit

Dynamically applying refresh overcharge voltage to extend refresh cycle time

Efficient clocking scheme for a bidirectional data link

SARASWAT RUCHIR

Energy efficient power distribution for 3D integrated circuit stack

Fully integrated voltage regulators for multi-stack integrated circuit architectures

BAYERISCHE MOTOREN WERKE AG

Three-plate pressure die casting mold having improved sprue separation, and method for pressure die casting

Three-plate pressure die casting mold having improved sprue separation, and method for pressure die casting (II)

DROEGE GUIDO

Interlayer communications for 3D integrated circuit stack

TAHOE RES LTD

Stacked memory with interface providing offset interconnects

LIU TSUN HO

Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems

VOGT PETE

Stacked memory with interface providing offset interconnects

QIMONDA AG

Semiconductor memory system and semiconductor memory chip