Inventor

RAJ ASHOK

US52 patents

⚠️ This page may combine multiple inventors who share the name “RAJ ASHOK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJ ASHOK

INTEL CORP

Cluster with multiple paths between hosts and I/O controllers

Method and computer program for data conversion in a heterogeneous communications network

Mechanism for allowing multiple entities on the same host to handle messages of same service class in a cluster

Providing dedicated resources for a system management mode of a processor

Retargeting of platform interrupts

Network interface for data transport in heterogeneous computing environments

I/O translation lookaside buffer performance

Instruction and logic to expose error domain topology to facilitate failure isolation in a processor

Instruction and logic for machine check interrupt management

Apparatus and method to identify the source of an interrupt

Systems and method for dynamic address based mirroring

Management of processor performance based on user interrupts

Signaling software recoverable errors

Network interface for data transport in heterogeneous computing environments

Unified address translation for virtualization of input/output devices

Unified address translation for virtualization of input/output devices

Network interface for data transport in heterogeneous computing environments

Processing device, control unit, electronic device, method for the electronic device, and computer program for the electronic device

Unified address translation for virtualization of input/output devices

Address space identifier management in complex input/output virtualization environments

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

System, apparatus and method for providing hardware feedback information in a processor

Apparatus and method to identify the source of an interrupt

Apparatus and method to identify the source of an interrupt

Scalable access control checking for cross-address-space data movement

PASID granularity resource control for IOMMU

Pause communication from I/O devices supporting page faults

Allocating machine check architecture banks

Methods and apparatus to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset

Measuring per-node bandwidth within non-uniform memory access (NUMA) systems

Process address space identifier virtualization using hardware paging hint

Enforcing unique page table permissions with shared page tables

Determine when an error log was created

Hardware apparatuses and methods to check data storage devices for transient faults

Enabling error status and reporting in a machine check architecture

Handling of error prone cache line slots of memory side cache of multi-level system memory

Interfacing with block-based storage in a processor

Context based alert system

Hardware apparatuses and methods to check data storage devices for transient faults

Exchange error information from platform firmware to operating system

Determine when an error log was created

Device, method, and system to identify a page request to be processed after a reset event

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Apparatus and method for system physical address to memory module address translation

Hardware unit for reverse translation in a processor

Memory pressure notifier

Apparatus and method for performance state matching between source and target processors based on interprocessor interrupts

System and method to increase availability in a multi-level memory configuration

HOOT LIVE INC

Systems and methods for performing useful commissioned work using distributed networks

RAJ ASHOK

Mechanism for advanced server machine check recovery and associated system software enhancements