Inventor

PURAYATH VINOD R

US35 patents

⚠️ This page may combine multiple inventors who share the name “PURAYATH VINOD R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PURAYATH VINOD R

APPLIED MATERIALS INC

Integrated bit-line airgap formation and gate stack post clean

Dopant etch selectivity control

Integrated oxide and nitride recess for better channel contact in 3D architectures

Metal air gap

Flash gate air gap

Accommodating imperfectly aligned memory holes

Integrated bit-line airgap formation and gate stack post clean

Vertical gate separation

Air gaps between copper lines

Integrated oxide recess and floating gate fin trimming

3D flash memory cells which discourage cross-cell electrical tunneling

Accommodating imperfectly aligned memory holes

Accommodating imperfectly aligned memory holes

SANDISK TECHNOLOGIES INC

Three dimensional NAND device with birds beak containing floating gates and method of making thereof

Air gap isolation in non-volatile memory

Metal layer air gap formation

Three dimensional NAND device with birds beak containing floating gates and method of making thereof

Nanodot enhanced hybrid floating gate for non-volatile memory devices

Memory device with control gate oxygen diffusion control and method of making thereof

Non-volatile storage element with suspended charge storage region

Non-volatile storage element with suspended charge storage region

Inverted-T word line and formation for non-volatile storage

Semiconductor device with copper interconnects separated by air gaps

SANDISK 3D LLC

Resistance-switching memory cell with multiple raised structures in a bottom electrode

Resistance-switching memory cell with multiple raised structures in a bottom electrode

Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask

Process for forming resistive switching memory cells using nano-particles

SANDISK CORP

Dielectric layer above floating gate for reducing leakage current

Method of forming dielectric layer above floating gate for reducing leakage current

Non-volatile memory with sidewall channels and raised source/drain regions

PACHAMUTHU JAYAVEL

Air isolation in high density non-volatile memory

Process for fabricating non-volatile storage

MATAMIS GEORGE

Self-aligned three-dimensional non-volatile memory fabrication

PURAYATH VINOD R

Copper interconnects separated by air gaps and method of making thereof

KAI JAMES K

Non-volatile memory cell containing a nano-rail electrode