Inventor

LIU HUANG

US95 patents

⚠️ This page may combine multiple inventors who share the name “LIU HUANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU HUANG

GLOBALFOUNDRIES INC

Liner and cap layer for placeholder source/drain contact structure planarization and replacement

Methods for fabricating integrated circuits using self-aligned quadruple patterning

Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same

10 nm alternative N/P doped fin for SSRW scheme

Method for forming air gap structure using carbon-containing spacer

Metal resistor using FinFET-based replacement gate process

Integrated circuits having replacement gate structures and methods for fabricating the same

FinFET gate with insulated vias and method of making same

Shallow trench isolation integration methods and devices formed thereby

Method for eliminating interlayer dielectric dishing and controlling gate height uniformity

Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures

Integrated circuits having improved gate structures and methods for fabricating same

Method for reducing gate height variation due to overlapping masks

Methods for forming mask layers using a flowable carbon-containing silicon dioxide material

Dimension-controlled via formation processing

Methods for preventing oxidation damage during FinFET fabrication

Methods for fabricating integrated circuits utilizing silicon nitride layers

Shallow trench isolation integration methods and devices formed thereby

Method to improve selectivity cobalt cap process

Uniform gate height for mixed-type non-planar semiconductor devices

Modified, etch-resistant gate structure(s) facilitating circuit fabrication

Capping structure

Achieving a critical dimension target based on resist characteristics

Dimension-controlled via formation processing

Method of forming a dielectric film

Method of forming a low-K dielectric film

Through silicon via device having low stress, thin film gaps and methods for forming the same

Device with large EPI in FinFETs and method of manufacturing

CHARTERED SEMICONDUCTOR MFG

Two-step, low argon, HDP CVD oxide deposition process

Intermetal dielectric layer for integrated circuits

Method and apparatus for providing void structures

Method for reducing silicide defects in integrated circuits

Interconnect capping layer and method of fabrication

Intermetal dielectric layer for integrated circuits

GLOBALFOUNDRIES SG PTE LTD

Method for forming an air gap around a through-silicon via

Integrated circuit system employing sacrificial spacers

Reliable contacts

Method of forming high-k dielectric stop layer for contact hole opening

Reliable interconnect for semiconductor device

Integrated circuit including a stressed dielectric layer with stable stress

YU HONG

Method for forming an air gap around a through-silicon via

Integrated circuit system with via and method of manufacture thereof

Damascene process for aligning and bonding through-silicon-via based 3D integrated circuit stacks

Reliable contacts

HEFECHIP CORPORATION LTD

Semiconductor device for a volatile memory and method of manufacturing semiconductor device

Semiconductor device and fabrication method thereof

LIU HUANG

Integration of eNVM, RMG, and HKMG modules

MISHRA SHAILENDRA

Method of forming shallow trench isolation structures for integrated circuits

LEONG LUP SAN

Method for forming through silicon via with wafer backside protection

UNIV SOUTHWEST PETROLEUM

Gas based testing method for pore volume compressibility of low-permeability rock