Inventor

STARK GAVIN J

GB115 patents

⚠️ This page may combine multiple inventors who share the name “STARK GAVIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STARK GAVIN J

NETRONOME SYSTEMS INC

Modular and partitioned SDN switch

Method of detecting large flows within a switch fabric of an SDN switch

Picoengine instruction that controls an intelligent packet data register file prefetch function

Transactional memory that supports a put with low priority ring command

Script-controlled egress packet modifier

Executing a selected sequence of instructions depending on packet type in an exact-match flow switch

Crossbar and an egress packet modifier in an exact-match flow switch

SDN protocol message handling within a modular and partitioned SDN switch

Method of generating subflow entries in an SDN switch

Transactional memory that performs an atomic look-up, add and lock operation

Hash range lookup command

Multiprocessor system having fast clocking prefetch circuits that cause processor clock signals to be gapped

Multiprocessor system having efficient and shared atomic metering resource

Multiprocessor system having posted transaction bus interface that generates posted transaction bus commands

Configurable mesh data bus in an island-based network flow processor

Method of handling SDN protocol messages in a modular and partitioned SDN switch

Flow switch IC that uses flow IDs and an exact-match flow table

Making a flow ID for an exact-match flow table using a programmable reduce table circuit

Making a flow ID for an exact-match flow table using a byte-wide multiplexer circuit

Generating a flow ID by passing packet data serially through two CCT circuits

Slice-based intelligent packet data register file

Generating a hash using S-box nonlinearizing of a remainder input

Storing an entropy signal from a self-timed logic bit stream generator in an entropy storage ring

Intelligent packet data register file that prefetches data for future instruction execution

Entropy storage ring having stages with feedback inputs

Configuration mesh data bus and transactional memories in a multi-processor integrated circuit

Chained CPP command

Network interface device that alerts a monitoring processor if configuration of a virtual NID is changed

Network interface device that maps host bus writes of configuration information for virtual NIDs into a small transactional memory

Inter-packet interval prediction learning algorithm

Transactional memory that supports a put with low priority ring command

Self-timed logic bit stream generator with command to run for a number of state transitions

Transactional memory that performs an atomic metering command

Transactional memory that supports put and get ring commands

Configuration mesh data bus and transactional memories in a multi-processor integrated circuit

Flow control using a local event ring in an island-based network flow processor

Executing a selected sequence of instructions depending on packet type in an exact-match flow switch

STARK GAVIN J

Commonality of memory island interface and structure

Transactional memory that performs an atomic metering command

Configurable mesh control bus in an island-based network flow processor

Island-based network flow processor integrated circuit

Staggered island structure in an island-based network flow processor

Flow control using a local event ring in an island-based network flow processor

Network appliance that determines what processor to send a future packet to based on a predicted future arrival time

Recursive lookup with a hardware trie structure that has no sequential logic elements

INTEL CORP

MAC bus interface

Multiple coprocessor architecture to process a plurality of subtasks in parallel

NEUGEBAUER ROLF

Flow key lookup involving multiple simultaneous cam operations to identify hash values in a hash bucket

Flow key lookup involving multiple simultaneous cam operations to identify hash values in a hash bucket

VIRATA LTD

Method and apparatus for source rate pacing in an ATM network