Inventor
FERENCE THOMAS G
US28 patents
⚠️ This page may combine multiple inventors who share the name “FERENCE THOMAS G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS6265771B1Jul 24, 2001
Dual chip with heat sink
IBM209 citations99
US5926029AJul 20, 1999
Ultra fine probe contacts
IBM151 citations99
US6611050B1Aug 26, 2003
Chip edge interconnect apparatus and method
IBM79 citations98
US6271102B1Aug 7, 2001
Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
IBM125 citations98
US5972765AOct 26, 1999
Use of deuterated materials in semiconductor processing
IBM140 citations98
US5244143ASep 14, 1993
Apparatus and method for injection molding solder and applications thereof
IBM297 citations98
US6368881B1Apr 9, 2002
Wafer thickness control during backside grind
IBM54 citations96
US5903045AMay 11, 1999
Self-aligned connector for stacked chip module
IBM51 citations96
US6221775B1Apr 24, 2001
Combined chemical mechanical polishing and reactive ion etching process
IBM64 citations95
US6426241B1Jul 30, 2002
Method for forming three-dimensional circuitization and circuits formed
IBM39 citations93
US6915795B2Jul 12, 2005
Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
IBM20 citations92
US6887126B2May 3, 2005
Wafer thickness control during backside grind
IBM25 citations92
US6534389B1Mar 18, 2003
Dual level contacts and method for forming
IBM34 citations92
US6521977B1Feb 18, 2003
Deuterium reservoirs and ingress paths
IBM30 citations92
US6030855AFeb 29, 2000
Self-aligned connector for stacked chip module
IBM14 citations74
US5793103AAug 11, 1998
Insulated cube with exposed wire lead
IBM13 citations74
US6770501B2Aug 3, 2004
Deuterium reservoirs and ingress paths
IBM11 citations73
US6600213B2Jul 29, 2003
Semiconductor structure and package including a chip having chamfered edges
IBM7 citations73
US5609772AMar 11, 1997
Cube maskless lead open process using chemical mechanical polish/lead-tip expose process
IBM6 citations63
US6380063B1Apr 30, 2002
Raised wall isolation device with spacer isolated contacts and the method of so forming
IBM6 citations62
US7134933B2Nov 14, 2006
Wafer thickness control during backside grind
IBM0 citations52
TERACOMM RES INC
6 patentsUS6517944B1Feb 11, 2003
Multi-layer passivation barrier for a superconducting element
TERACOMM RES INC19 citations84
US6630426B1Oct 7, 2003
Method of increasing the critical temperature of a high critical temperature superconducting film and a superconducting structure made using the method
TERACOMM RES INC5 citations73
US6476956B1Nov 5, 2002
Fast optical modulator
TERACOMM RES INC13 citations72
US6813056B2Nov 2, 2004
High amplitude fast optical modulator
TERACOMM RES INC4 citations61
US6429958B1Aug 6, 2002
Extinction ratio optical communication device using superconducting films
TERACOMM RES INC5 citations61
US6838749B2Jan 4, 2005
Structures for increasing the critical temperature of superconductors
TERACOMM RES INC1 citations52