Inventor

AVCI UYGAR E

US88 patents

⚠️ This page may combine multiple inventors who share the name “AVCI UYGAR E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AVCI UYGAR E

INTEL CORP

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Vertical backend transistor with ferroelectric material

Three-dimensional nanoribbon-based dynamic random-access memory

Three-dimensional ferroelectric NOR-type memory

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Reduced scale resonant tunneling field effect transistor

One transistor and one ferroelectric capacitor memory cells in diagonal arrangements

Anti-ferroelectric capacitor memory cell

Transistors with metal source and drain contacts including a Heusler alloy

Semiconductor devices with metal contacts including crystalline alloys

One transistor and ferroelectric FET based memory cell

Polarization gate stack SRAM

Transistor threshold voltage variation optimization

Polarization gate stack SRAM

Non-volatile ferroelectric logic with granular power-gating

Tunnel field-effect transistor (TFET) based high-density and low-power sequential

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

Multilayer insulator stack for ferroelectric transistor and capacitor

Capacitor with dual dielectric layers

Stacked 2D CMOS with inter metal layers

Tunneling field effect transistors

Magnetic and spin logic devices based on Jahn-Teller materials

Capacitor with an electrically conductive layer coupled with a metal layer of the capacitor

Thin film transistors having semiconductor structures integrated with 2D channel materials

TMD inverted nanowire integration

Angled etch to enable tin removal from selected sidewalls

Capacitors with built-in electric fields

Three-dimensional nanoribbon-based dynamic random-access memory

Multi-level spin logic

TMD inverted nanowire integration

Charge-transfer spacers for stacked nanoribbon 2D transistors

Floating body memory cell having gates favoring different conductivity type regions

FeFET with embedded conductive sidewall spacers and process for forming the same

Trench capacitor with extended dielectric layer

Ultra-dense ferroelectric memory with self-aligned patterning

Metal insulator transition field programmable routing block

Memory cell with a ferroelectric capacitor integrated with a transtor gate

Logic-embedded diode/tunnel diode coupled to floating gate with I-V characteristics suitable for logic state retention

Floating body memory cell having gates favoring different conductivity type regions

CHANG PETER L D

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

Floating body memory cell having gates favoring different conductivity type regions

KOTLYAR ROZA

Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs