Inventor

SIAH SOH YUN

SG28 patents

⚠️ This page may combine multiple inventors who share the name “SIAH SOH YUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIAH SOH YUN

GLOBALFOUNDRIES SG PTE LTD

Top electrode dome formation

Integrated circuits including a dummy metal feature and methods of forming the same

Integrated two-terminal device with logic device for embedded application

Integrated two-terminal device with logic device for embedded application

Memory device with dielectric blocking layer for improving interpoly dielectric breakdown

Neuromorphic memories with split gate flash multi-level cell and method of making the same

Shielded MRAM cell

Method of forming split-gate cell for non-volative memory devices

Cost-effective method to form a reliable memory device with selective silicidation and resulting device

Dielectric posts in metal layers

Method of forming split-gate cell for non-volative memory devices

Plasma discharge path

Method for producing integrated circuit memory cells with less dedicated lithographic steps

CHARTERED SEMICONDUCTOR MFG

Salicide formation on narrow poly lines by pulling back of spacer

Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices

Method to form shallow trench isolations with rounded corners and reduced trench oxide recess

Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts

Partially recessed shallow trench isolation method for fabricating borderless contacts

Method of making low-leakage architecture for sub-0.18 μm salicided CMOS device

Method of forming a high performance and low cost CMOS device

Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape

Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts

Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication

Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application

Method of forming shallow trench isolation regions with improved corner rounding

TAN JUAN BOON

Back-side MOM/MIM devices

Device with integrated power supply

LI LIANG

Methods of protecting elevated polysilicon structures during etching processes