Inventor

WISNIEWSKI ROBERT W

US46 patents

⚠️ This page may combine multiple inventors who share the name “WISNIEWSKI ROBERT W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WISNIEWSKI ROBERT W

IBM

Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint

Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements

Mechanism to save and restore cache and translation trace for fast context switch

Location-based vehicle powertrain regulation system

Location-based vehicle powertrain regulation system

Operating system thread scheduling for optimal heat dissipation

Method for vertical integrated performance and environment monitoring

Color-based cache monitoring

Method and system for predicting the performance benefits of mapping subsets of application data to multiple page sizes

Virtual meetings

Latency-aware thread scheduling in non-uniform cache architecture systems

Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache

System and method for networking educational equipment

Method and apparatus for a hierarchical synchronization barrier in a multi-node system

Virtual meetings

Location-based vehicle powertrain regulation system

Providing navigational support through corrective data

Hardware support for software controlled fast multiplexing of performance counters

SALAPURA VALENTINA

Hardware enabled performance counters with support for operating system context switching

Hardware support for software controlled fast reconfiguration of performance counters

Method and apparatus for a hierarchical synchronization barrier in a multi-node system

Hardware support for software controlled fast multiplexing of performance counters

Hardware support for software controlled fast reconfiguration of performance counters

SHEN XIAOWEI

System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory

Architecture support of memory access coloring

Cache coherence monitoring and feedback

MAMIDALA AMITH R

Mechanisms for efficient intra-die/intra-chip collective messaging

Mechanisms for efficient intra-die/intra-chip collective messaging

Mechanism for optimized intra-die inter-nodelet messaging communication

KRIEGER ORRAN Y

Prefetch engine based translation prefetching

Quality of service scheduling for simultaneous multi-threaded processors

Scheduling threads having complementary functional unit usage on SMT processors

GARA ALAN

Using DMA for copying performance counter data to memory

Using DMA for copying performance counter data to memory

Hardware support for collecting performance counters directly to memory

TREMAINE ROBERT B

Memory page management in a tiered memory system

Memory architecture with policy based data storage

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer

FRANKE HUBERTUS

Method to embed a light-weight kernel in a full-weight kernel to provide a heterogeneous execution environment

TSAFRIR DAN

Method for guaranteeing program correctness using fine-grained hardware speculative execution

WISNIEWSKI ROBERT W

Communication tagging

INGLETT TODD A

Method to utilize cores in different operating system partitions

CHAAR JARIR KAMEL

Methods and apparatus for managing and distinguishing instant messaging sessions and threads

COLE CLEMENT T

Scalable synchronization mechanism for distributed memory

DOZSA GABOR J

Message passing with queues and channels