Inventor

NAVEH ALON

US101 patents

⚠️ This page may combine multiple inventors who share the name “NAVEH ALON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAVEH ALON

INTEL CORP

Power management coordination in multi-core processors

Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active cores

Mechanism for processor power state aware distribution of lowest priority interrupt

Active state link power management

Coordinating idle state transitions in multi-core processors

Method, system, and apparatus for rerouting interrupts in a multi-core processor

Active state link power management

System and method of coherent data transfer during processor idle states

Controlling standby power of low power devices

Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device

Method and apparatus for performance effective power throttling

Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device

Simultaneous multi-voltage rail voltage regulation messages

Method and apparatus for controlling power management state transitions

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Dynamically controlling cache size to maximize energy efficiency

Dynamically controlling cache size to maximize energy efficiency

Techniques and system for managing platform temperature

System and method of message-based power management

Power aware software pipelining for hardware accelerators

Systems and methods for communicating voltage regulation information between a voltage regulator and an integrated circuit

P-state feedback to operating system with hardware coordination

Managing power consumption in a multi-core processor

Mechanism for processor power state aware distribution of lowest priority interrupts

Active state link power management

Low latency buffer control system and method

Multi-level CPU high current protection

Operating point management in multi-core architectures

User level control of power management policies

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Providing an interface for demotion control information in a processor

Method for booting a heterogeneous system and presenting a symmetric core view

Apparatus and method for heterogeneous processors mapping to virtual cores

Hetergeneous processor apparatus and method

ROTEM EFRAIM

Method and apparatus to control power consumption of a plurality of processor cores

Operating point management in multi-core architectures

Controlling current transients in a processor

Extension of CPU context-state management for micro-architecture state

NAVEH ALON

Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates

Power management coordination in multi-core processors

Migrating tasks between asymmetric computing elements of a multi-core processor

ANANTHAKRISHNAN AVINASH N

Dynamically controlling cache size to maximize energy efficiency

Estimating temperature of a processor core in a low power state without thermal sensor information

FETZER ERIC

Managing power consumption in a multi-core processor

SODHI INDER M

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

SISTLA KRISHNAKANTH V

User level control of power management policies

GINZBURG BORIS

Providing an asymmetric multicore processor system transparently to an operating system

JAHAGIRDAR SANJEEV

Method and apparatus for powered off processor core mode

OFFEN ZEEV

Method and apparatus for MONITOR and MWAIT in a distributed cache architecture

QUALCOMM INC

Merging of power events related to estimated power consumption of different devices in a hierarchical power management system in an integrated circuit (IC) chip to perform power throttling