Inventor

DRAPALA GARRETT M

US32 patents

⚠️ This page may combine multiple inventors who share the name “DRAPALA GARRETT M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DRAPALA GARRETT M

IBM

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Maintaining order with parallel access data streams

Memory controlled operations under dynamic relocation of storage

Granting exclusive cache access using locality cache coherency state

Granting exclusive cache access using locality cache coherency state

Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing

Designated cache data backup during system operation

Non-data inclusive coherent (NIC) directory for cache

Non-data inclusive coherent (NIC) directory for cache

Method, system, and computer program product for pipeline arbitration

Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer

Dynamic data transfer control method and apparatus for shared SMP computer systems

Dynamic relocation of storage

Multilevel cache hierarchy for finding a cache line on a remote node

Granting exclusive cache access using locality cache coherency state

Operations interlock under dynamic relocation of storage

Matrix and compression-based error detection

Matrix and compression-based error detection

Storage system that prioritizes storage requests

Early shared resource release in symmetric multiprocessing computer systems

Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer

DRAPALA GARRETT M

Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system

Main memory operations in a symmetric multiprocessing computer

Controlling data stream interruptions on a shared interface

Centralized serialization of requests in a multiprocessor system

BRONSON TIMOTHY C

Multilevel cache hierarchy for finding a cache line on a remote node

Cache bank modeling with variable access and busy times

BLAKE MICHAEL A

Maintaining cache coherence in a multi-node, symmetric multiprocessing computer

Maintaining cache coherence in a multi-node, symmetric multiprocessing computer

DUNN BERGER DEANNA POSTLES

Management of multipurpose command queues in a multilevel cache hierarchy