Inventor

FEE MICHAEL F

US40 patents

⚠️ This page may combine multiple inventors who share the name “FEE MICHAEL F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FEE MICHAEL F

IBM

System, method and computer program product for providing a new quiesce state

Position-based replacement policy for address synonym management in shared caches

Memory controlled operations under dynamic relocation of storage

Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing

Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy

Configuration based cache coherency protocol selection

Managing quiesce requests in a multi-processor environment

Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy

Method, system, and computer program product for pipeline arbitration

Reducing penalties for cache accessing operations

Dynamic cache row fail accumulation due to catastrophic failure

Dynamic cache row fail accumulation due to catastrophic failure

Dynamic cache row fail accumulation due to catastrophic failure

Configuration based cache coherency protocol selection

Configuration based cache coherency protocol selection

Configuration based cache coherency protocol selection

Mitigating busy time in a high performance cache

Mitigating busy time in a high performance cache

Managing in-line store throughput reduction

Dynamic mode transitions for cache instructions

Dynamic partial blocking of a cache ECC bypass

Dynamic partial blocking of a cache ECC bypass

Reducing store operation busy times

Configuration based cache coherency protocol selection

Managing quiesce requests in a multi-processor environment

Cross-pipe serialization for multi-pipeline processor

BERGER DEANNA P

Managing in-line store throughput reduction

Mitigating busy time in a high performance cache

Recover store data merging

Dynamically supporting variable cache array busy and access times for a targeted interleave

DUNN BERGER DEANNA POSTLES

Management of multipurpose command queues in a multilevel cache hierarchy

System, apparatus and method utilizing early access to shared cache pipeline for latency reduction

Dynamic mode transitions for cache instructions

BERGER DEANNA POSTLES DUNN

Cross-pipe serialization for multi-pipeline processor

Reducing store operation busy times

CONKLIN CHRISTOPHER R

Updating settings of a processor core concurrently to the operation of a multi core processor system

BLAKE MICHAEL A

Tracking dynamic memory reallocation using a single storage address configuration table

O'NEILL JR ARTHUR J

Least recently used (LRU) compartment capture in a cache memory system

FEE MICHAEL F

Reducing penalties for cache accessing operations

STRAIT GARY E

Method, system and computer program product for data buffers partitioned from a cache array