Inventor

SONNELITTER III ROBERT J

US71 patents

⚠️ This page may combine multiple inventors who share the name “SONNELITTER III ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SONNELITTER III ROBERT J

IBM

Controller address contention assumption

Nested cache coherency protocol in a tiered multi-node computer system

Nested cache coherency protocol in a tiered multi-node computer system

Position-based replacement policy for address synonym management in shared caches

Speculative data return concurrent to an exclusive invalidate request

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

Maintaining order with parallel access data streams

Memory controlled operations under dynamic relocation of storage

Controller address contention assumption

Non-disruptive clearing of varying address ranges from cache

Non-disruptive clearing of varying address ranges from cache

Non-disruptive clearing of varying address ranges from cache

Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing

Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy

Dynamic cache queue allocation based on destination availability

Target cache line arbitration within a processor cluster

Multilevel cache eviction management

Configuration based cache coherency protocol selection

EDRAM refresh in a high performance cache architecture

Methods, systems, and computer program products for recovering from branch prediction latency

Castout handling in a distributed cache topology

Preinstall of partial store cache lines

Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy

Vector in restricted memory to track remote copies

Remote access array

Efficient eviction of whole set associated cache or selected range of addresses

Method, system, and computer program product for merging data

Method, system and computer program product for an implicit predicted return from a predicted subroutine

System coherency protocol

Configuration based cache coherency protocol selection

Configuration based cache coherency protocol selection

Configuration based cache coherency protocol selection

Mitigating busy time in a high performance cache

Mitigating busy time in a high performance cache

Managing in-line store throughput reduction

Dynamic mode transitions for cache instructions

Lateral persistence directory states

Efficient inclusive cache management

DUNN BERGER DEANNA POSTLES

Management of multipurpose command queues in a multilevel cache hierarchy

System, apparatus and method utilizing early access to shared cache pipeline for latency reduction

Dynamic mode transitions for cache instructions

AMBROLADZE EKATERINA M

Dynamic multi-level cache including resource access fairness scheme

Monitoring processing time in a shared pipeline

FEE MICHAEL

eDRAM refresh in a high performance cache architecture

ALEXANDER KHARY J

System and method for Controlling restarting of instruction fetching using speculative address computations

ORF DIANA L

Dynamic cache queue allocation based on destination availability

BERGER DEANNA POSTLES DUNN

Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interface

COLLURA ADAM B

Clock-based debugging for embedded dynamic random access memory element in a processor core

BERGER DEANNA P

Managing in-line store throughput reduction