Inventor

EKANADHAM KATTAMURI

US52 patents

⚠️ This page may combine multiple inventors who share the name “EKANADHAM KATTAMURI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EKANADHAM KATTAMURI

IBM

Method for resource control in parallel environments using program organization and run-time support

Method for resource control in parallel environments using program organization and run-time support

Self-parallelizing computer system and method

Optimized system for analytics (graphs and sparse matrices) operations

Method of maintaining data coherency in a computer system having a plurality of interconnected nodes

Explicit coherence using split-phase controls

Memory transaction having implicit ordering effects

Integrated communications for pipelined computers

Apparatus for parallelizing serial instruction sequences and creating entry points into parallelized instruction sequences at places other than beginning of particular parallelized instruction sequence

Self-scheduling parallel computer system and method

Home node migration for distributed shared memory systems

Scalable memory

Context oriented branch history table

Method of self-parallelizing and self-parallelizing multiprocessor using the method

Prefetching indirect array accesses

Methods, systems and computer program products for concomitant pair prefetching

Sophisticated run-time system for graph processing

Sophisticated run-time system for graph processing

Optimized system for analytics (graphs and sparse matrices) operations

Multi-processor cache coherency protocol allowing asynchronous modification of cache data

Control flow based compression of execution traces

Redundant transactions for detection of timing sensitive errors

Memory transaction having implicit ordering effects

System and method for supporting secure objects using a memory access control monitor

Scalable processor

Memoryless communications adapter including queueing and matching primitives for scalable distributed parallel computer systems

Transactions for checkpointing and reverse execution

Loosely-coupled slice target file data

Instruction fusion using dependence analysis

Efficient performance of inner loops on a multi-lane processor

Reformatting matrices to improve computing efficiency

Encrypted data processing design including local buffers

Memory access operations for large graph analytics

Supporting large-word operations in a reduced instruction set computer (“RISC”) processor

Reformatting matrices to improve computing efficiency

Processor core design optimized for machine learning applications

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

Detection of hardware errors using redundant transactions for system test

Redundant transactions for detection of timing sensitive errors

Comparing hash values computed at function entry and exit for increased security

Mechanism for instruction fusion using tags

Maintaining data coherence by using data domains

Encrypted data processing design including cleartext register files

EKANADHAM KATTAMURI

Operating a stack of information in an information handling system

Seamless interface for multi-threaded core accelerators

Enhancing timeliness of cache prefetching

Event tracking hardware

Maintaining data coherence by using data domains

CHUNG I-HSIN

Binary programmable method for application performance data collection

Profiling application performance according to data structure