P

Inventor

MOREIRA JOSE EDUARDO

US18 patents

Patents

18 patents
US6321373B1Nov 20, 2001

Method for resource control in parallel environments using program organization and run-time support

IBM169 citations98
US5978583ANov 2, 1999

Method for resource control in parallel environments using program organization and run-time support

IBM162 citations98
US9304835B1Apr 5, 2016

Optimized system for analytics (graphs and sparse matrices) operations

IBM48 citations97
US6343375B1Jan 29, 2002

Method for optimizing array bounds checks in programs

IBM75 citations95
US9690586B2Jun 27, 2017

Processing of multiple instruction streams in a parallel slice processor

IBM26 citations94
US9690585B2Jun 27, 2017

Parallel slice processor with dynamic instruction stream mapping

IBM22 citations94
US9672043B2Jun 6, 2017

Processing of multiple instruction streams in a parallel slice processor

IBM29 citations94
US9665372B2May 30, 2017

Parallel slice processor with dynamic instruction stream mapping

IBM25 citations94
US9977678B2May 22, 2018

Reconfigurable parallel execution and load-store slice processor

IBM7 citations84
US9971602B2May 15, 2018

Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices

IBM6 citations84
US9778967B2Oct 3, 2017

Sophisticated run-time system for graph processing

IBM8 citations83
US9772890B2Sep 26, 2017

Sophisticated run-time system for graph processing

IBM10 citations83
US9400700B2Jul 26, 2016

Optimized system for analytics (graphs and sparse matrices) operations

IBM11 citations83
US10983800B2Apr 20, 2021

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

IBM2 citations73
US10157064B2Dec 18, 2018

Processing of multiple instruction streams in a parallel slice processor

IBM2 citations73
US10083039B2Sep 25, 2018

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

IBM3 citations73
US10219556B2Mar 5, 2019

Actively controlled performance clothing

IBM2 citations69
US10884942B2Jan 5, 2021

Reducing memory access latency in scatter/gather operations

IBM0 citations51