P

Inventor

FAIS YANIV

IL31 patents
⚠️ This page may combine multiple inventors who share the name “FAIS YANIV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

27 patents
US10372416B2Aug 6, 2019

Multiply-accumulate “0” data gating

INTEL CORP15 citations93
US11494608B2Nov 8, 2022

Methods and apparatus to tile walk a tensor for convolution operations

INTEL CORP6 citations85
US11037330B2Jun 15, 2021

Low rank matrix compression

INTEL CORP10 citations85
US10467795B2Nov 5, 2019

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

INTEL CORP6 citations83
US11704564B2Jul 18, 2023

Real time context dependent deep learning

INTEL CORP1 citations72
US11620766B2Apr 4, 2023

Low rank matrix compression

INTEL CORP1 citations72
US11600035B2Mar 7, 2023

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

INTEL CORP1 citations72
US11087206B2Aug 10, 2021

Smart memory handling and data management for machine learning networks

INTEL CORP3 citations72
US10922556B2Feb 16, 2021

Storage system of DNN outputs for black box

INTEL CORP4 citations72
US10853035B2Dec 1, 2020

Multiply-accumulate “0” data gating

INTEL CORP2 citations72
US10606559B2Mar 31, 2020

Multiply-accumulate “0” data gating

INTEL CORP1 citations72
US11238338B2Feb 1, 2022

Real time context dependent deep learning

INTEL CORP3 citations71
US11599777B2Mar 7, 2023

Scheduling configuration for deep learning networks

INTEL CORP3 citations70
US12223413B2Feb 11, 2025

Methods and apparatus to tile walk a tensor for convolution operations

INTEL CORP0 citations62
US12223427B2Feb 11, 2025

Real time context dependent deep learning

INTEL CORP0 citations62
US12131507B2Oct 29, 2024

Low rank matrix compression

INTEL CORP0 citations62
US12112251B2Oct 8, 2024

Methods and apparatus to tile walk a tensor for convolution operations

INTEL CORP0 citations62
US11886984B2Jan 30, 2024

Variable precision and mix type representation of multiple layers in a network

INTEL CORP0 citations62
US11763140B2Sep 19, 2023

Smart memory handling and data management for machine learning networks

INTEL CORP0 citations62
US11669719B2Jun 6, 2023

Storage system of DNN outputs for black box

INTEL CORP0 citations62
US11656846B2May 23, 2023

Multiply-accumulate “0” data gating

INTEL CORP0 citations62
US11250610B2Feb 15, 2022

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

INTEL CORP0 citations62
US11093822B2Aug 17, 2021

Variable precision and mix type representation of multiple layers in a network

INTEL CORP1 citations62
US10990399B2Apr 27, 2021

Methods and apparatus to implement efficient communications between components of computing systems

INTEL CORP0 citations62
US12033063B2Jul 9, 2024

Scheduling configuration for deep learning networks

INTEL CORP0 citations59
US10762685B2Sep 1, 2020

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

INTEL CORP0 citations51
US12131250B2Oct 29, 2024

Inner product convolutional neural network accelerator

INTEL CORP0 citations47

MOBILEYE VISION TECHNOLOGIES LTD

3 patents

FREESCALE SEMICONDUCTOR INC

1 patent