Inventor

CHOWDHURY MURSHED

US29 patents

⚠️ This page may combine multiple inventors who share the name “CHOWDHURY MURSHED”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOWDHURY MURSHED

SANDISK TECHNOLOGIES LLC

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Concurrent formation of memory openings and contact openings for a three-dimensional memory device

Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof

Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same

Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings

Three-dimensional memory device with thickened word lines in terrace region

Concurrent formation of memory openings and contact openings for a three-dimensional memory device

High voltage field effect transistor with laterally extended gate dielectric and method of making thereof

Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof

Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes

Three-dimensional device with bonded structures including a support die and methods of making the same

Through-array conductive via structures for a three-dimensional memory device and methods of making the same

Method for removing a bulk substrate from a bonded assembly of wafers

Three-dimensional memory device with thickened word lines in terrace region and method of making thereof

Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same

Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Three-dimensional array device having a metal containing barrier and method of making thereof

Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes

Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same

Method for removing a bulk substrate from a bonded assembly of wafers

Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same

SANDISK TECHNOLOGIES INC

Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad

Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same

Monolithic three-dimensional NAND strings and methods of fabrication thereof

Select gate transistor with single crystal silicon for three-dimensional memory

Three dimensional NAND memory device with common bit line for multiple NAND strings in each memory block