Inventor

RAIKIN SHLOMO

IL68 patents

⚠️ This page may combine multiple inventors who share the name “RAIKIN SHLOMO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAIKIN SHLOMO

MELLANOX TECHNOLOGIES LTD

Address translation services for direct accessing of local memory over a network fabric

Efficient transport flow processing on an accelerator

Host bus access by add-on devices via a network interface controller

Network-based computational accelerator

Direct access to local memory in a PCI-E device

Storage system and server

Accessing remote storage devices using a local bus protocol

Direct IO access from a CPU&#39;s instruction stream

Page resolution status reporting

Control of persistent memory via a computer bus

NIC with switching functionality between network ports

Remote transactional memory

Accelerating and offloading lock access over a network

Network-attached memory

Caching policy in a multicore system on a chip (SOC)

INTEL CORP

Hybrid exclusive multi-level memory architecture with memory management

Protected cache architecture and secure programming paradigm to protect applications

Selective hardware lock disabling

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Scatter using index array and finite state machine

Gather using index array and finite state machine

Gather using index array and finite state machine

Apparatus and method for detecting and recovering from data fetch errors

Apparatus and method for detecting and recovering from data fetch errors

Apparatus and method for page walk extension for enhanced security checks

Posting weakly ordered transactions

SHEAFFER GAD

Registering a user-handler in hardware for transactional memory event handling

Metaphysical address space for holding lossy metadata in hardware

Extending cache coherency protocols to support locally buffered data

Read and write monitoring attributes in transactional memory (TM) systems

Read and write monitoring attributes in transactional memory (TM) systems

Memory model for hardware attributes within a transactional memory system

Memory model for hardware attributes within a transactional memory system

HABANA LABS LTD

Tensor-based memory access

Data compression scheme utilizing a repetitive value within the data stream

Method for remote direct memory access (RDMA) congestion control over an ethernet network

Approximation of mathematical functions in a vector processor

Activation function approximation in deep neural networks using rectified-linear-unit function

In-network computing with reduction operation by switch

RAIKIN SHLOMO

Gather cache architecture

Live lock free priority scheme for memory transactions in transactional memory

Protecting private data from cache attacks

Apparatus and method for memory-hierarchy aware producer-consumer instruction

SPERBER ZEEV

Gather using index array and finite state machine

Scatter using index array and finite state machine

GUERON SHAY

Obscuring memory access patterns in conjunction with deadlock detection or avoidance

SAGER DAVID J

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

MICROSOFT CORP

Metaphysically addressed cache metadata

PARDO ILAN

Snoop filter having centralized translation circuitry and shadow tag array

HILDESHEIM GUR

Virtual memory address range register

Direct IO access from a CPU's instruction stream