P

Inventor

ROZAS CARLOS

US24 patents
⚠️ This page may combine multiple inventors who share the name “ROZAS CARLOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

22 patents
US7472285B2Dec 30, 2008

Apparatus and method for memory encryption with reduced decryption latency

INTEL CORP66 citations98
US6725373B2Apr 20, 2004

Method and apparatus for verifying the integrity of digital objects using signed manifests

INTEL CORP84 citations95
US11651112B2May 16, 2023

Enabling stateless accelerator designs shared across mutually-distrustful tenants

INTEL CORP8 citations93
US7380049B2May 27, 2008

Memory protection within a virtual partition

INTEL CORP38 citations92
US11354482B2Jun 7, 2022

Enabling stateless accelerator designs shared across mutually-distrustful tenants

INTEL CORP2 citations83
US9407636B2Aug 2, 2016

Method and apparatus for securely saving and restoring the state of a computing platform

INTEL CORP13 citations83
US9355262B2May 31, 2016

Modifying memory permissions in a secure processing environment

INTEL CORP11 citations83
US7739466B2Jun 15, 2010

Method and apparatus for supporting immutable memory

INTEL CORP17 citations83
US7827550B2Nov 2, 2010

Method and system for measuring a program using a measurement agent

INTEL CORP8 citations79
US10970390B2Apr 6, 2021

Mechanism to prevent software side channels

INTEL CORP2 citations72
US9698989B2Jul 4, 2017

Feature licensing in a secure processing environment

INTEL CORP2 citations72
US9519803B2Dec 13, 2016

Secure environment for graphics processing units

INTEL CORP5 citations72
US10922088B2Feb 16, 2021

Processor instruction support to defeat side-channel attacks

INTEL CORP2 citations70
US11681533B2Jun 20, 2023

Restricted speculative execution mode to prevent observable side effects

INTEL CORP0 citations60
US12561144B1Feb 24, 2026

Circuitry and methods for a conditional fence instruction

INTEL CORP0 citations57
US12001346B2Jun 4, 2024

Device, method and system to supplement a skewed cache with a victim cache

INTEL CORP0 citations56
US9971705B2May 15, 2018

Virtual memory address range register

INTEL CORP0 citations51
US9769129B2Sep 19, 2017

Mutually assured data sharing between distrusting parties in a network environment

INTEL CORP0 citations51
US9684608B2Jun 20, 2017

Maintaining a secure processing environment across power cycles

INTEL CORP1 citations51
US9171163B2Oct 27, 2015

Mutually assured data sharing between distrusting parties in a network environment

INTEL CORP1 citations51
US11797309B2Oct 24, 2023

Apparatus and method for speculative execution information flow tracking

INTEL CORP0 citations48
US9729309B2Aug 8, 2017

Securing data transmission between processor packages

INTEL CORP0 citations41

SCARLATA VINCENT R

1 patent

HILDESHEIM GUR

1 patent