Inventor
DERRICK JOHN EDWARD
US16 patents
Patents
16 patentsUS6574727B1Jun 3, 2003
Method and apparatus for instruction sampling for performance monitoring and debug
IBM136 citations97
US5787486AJul 28, 1998
Bus protocol for locked cycle cache hit
IBM77 citations95
US5659710AAug 19, 1997
Cache coherency method and system employing serially encoded snoop responses
IBM143 citations94
US6442675B1Aug 27, 2002
Compressed string and multiple generation engine
IBM31 citations92
US6345356B1Feb 5, 2002
Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs
IBM21 citations92
US6286094B1Sep 4, 2001
Method and system for optimizing the fetching of dispatch groups in a superscalar processor
IBM23 citations92
US6240507B1May 29, 2001
Mechanism for multiple register renaming and method therefor
IBM26 citations88
US6321380B1Nov 20, 2001
Method and apparatus for modifying instruction operations in a processor
IBM18 citations84
US6289428B1Sep 11, 2001
Superscaler processor and method for efficiently recovering from misaligned data addresses
IBM16 citations84
US6425069B1Jul 23, 2002
Optimization of instruction stream execution that includes a VLIW dispatch group
IBM10 citations73
US6385719B1May 7, 2002
Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor
IBM12 citations73
US6336182B1Jan 1, 2002
System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch
IBM11 citations72
US5906659AMay 25, 1999
Computer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accesses
IBM9 citations71
US6430678B1Aug 6, 2002
Scoreboard mechanism for serialized string operations utilizing the XER
IBM3 citations62
US6304959B1Oct 16, 2001
Simplified method to generate BTAGs in a decode unit of a processing system
IBM3 citations62
US5983025ANov 9, 1999
Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses
IBM4 citations60