Inventor

YE SENG KIM

SG40 patents

⚠️ This page may combine multiple inventors who share the name “YE SENG KIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YE SENG KIM

MICRON TECHNOLOGY INC

Stacked semiconductor die assemblies with die support members and associated systems and methods

Memory devices with controllers under memory packages and associated systems and methods

Stacked semiconductor die assemblies with support members and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods

Through stack bridge bonding devices and associated methods

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods

Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer

Stacked semiconductor die assemblies with support members and associated systems and methods

Memory devices with controllers under memory packages and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods

Stacked semiconductor die assemblies with support members and associated systems and methods

Memory devices with controllers under memory packages and associated systems and methods

Nested semiconductor assemblies and methods for making the same

Surface mount device bonded to an inner layer of a multi-layer substrate

Multi-role semiconductor device substrates, semiconductor device assemblies employing the same, and methods for forming the same

Semiconductor assemblies with systems and methods for managing high die stack structures

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods

Three-dimensional bonding scheme and associated systems and methods

Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods

Stacked semiconductor die assemblies with support members and associated systems and methods

Stacked semiconductor die assemblies with die support members and associated systems and methods

Surface mount device bonded to an inner layer of a multi-layer substrate

Semiconductor assemblies with systems and methods for managing high die stack structures

Memory devices with controllers under memory packages and associated systems and methods

Semiconductor devices with multiple substrates and die stacks

Stacked semiconductor die assemblies with die support members and associated systems and methods

Multi-chip package with enhanced conductive layer adhesion

Dielectric interposer with electrical-connection cut-in

Wire bonding for stacked memory dies

Flexible interposer for semiconductor dies

Stacked capacitors for semiconductor devices and associated systems and methods

Package substrate for a semiconductor device

Three dimensional semiconductor trace length matching and associated systems and methods

Apparatus including direct-contact heat paths and methods of manufacturing the same

Cross stack bridge bonding devices and associated methods

Wire bonding directly on exposed conductive vias and interconnects and related systems and methods

Split via structure for semiconductor device packaging

Systems and methods for reducing the size of a semiconductor assembly

LOW PENG WANG

Microelectronic packages with small footprints and associated methods of manufacturing