Inventor

CHAN VEI-HAN

US49 patents

⚠️ This page may combine multiple inventors who share the name “CHAN VEI-HAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAN VEI-HAN

ADVANCED MICRO DEVICES INC

Multiple byte channel hot electron programming using ramped gate and source bias voltage

Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide

Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device

Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device

Memory cell programming with controlled current injection

Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration

Method for programming flash electrically erasable programmable read-only memory

Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM

Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Method and system for providing a drain side pocket implant

Method and system for source only reoxidation after junction implant for flash memory devices

Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

MOSEL VITELIC INC

Nonvolatile memories with floating gate spacers, and methods of fabrication

Nonvolatile memories with floating gate spacers, and methods of fabrication

Nonvolatile memory structures and access methods

Nonvolatile memory with pedestals

Nonvolatile memory structures and fabrication methods

Nonvolatile memory structures and fabrication methods

Nonvolatile memory structures and access methods

APLUS FLASH TECHNOLOGY INC

Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration

Stacked gate flash memory cell with reduced disturb conditions

Array architecture and process flow of nonvolatile memory devices for mass storage applications

Erase condition for flash memory

Array architecture and process flow of nonvolatile memory devices for mass storage applications

Breakdown-free high voltage input circuitry

PROMOS TECHNOLOGIES INC

Atomic layer deposition of interpoly oxides in a non-volatile memory device

Method of forming ONO-type sidewall with reduced bird&#39;s beak

Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate

Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate

Nonvolatile memory structures and fabrication methods

KORDUS II LOUIS CHARLES

Multi-terminal phase change devices

Multi-terminal phase change devices

Multi-terminal phase change devices

Method for selectively establishing an electrical connection in a multi-terminal phase change device

MICROSOFT TECHNOLOGY LICENSING LLC

CMOS image sensor with a reduced likelihood of an induced electric field in the epitaxial layer

Micro lens sensor having micro lens heights that vary based on image height

Micro lens time-of-flight sensor having micro lens heights that vary based on image height

Time-of-flight RGB-IR image sensor

AMIC TECHNOLOGY INC

Flash memory cell &amp; array with improved pre-program and erase characteristics

Flash EPROM using junction hot hole injection for erase

AGATE LOGIC INC

Methods for fabricating multi-terminal phase change devices

Reconfigurable logic structures

CSWITCH CORP

Reconfigurable logic structures

CHAN VEI-HAN

Field-programmable gate array having voltage identification capability

CSWITCH INC

Methods for fabricating multi-terminal phase change devices

AGATA LOGIC INC

SEU hardened latches and memory cells using programmable resistance devices

OLIVA ANTONIETTA

Impedance matching and trimming apparatuses and methods using programmable resistance devices

Method of forming ONO-type sidewall with reduced bird's beak

Flash memory cell & array with improved pre-program and erase characteristics