Inventor

MATHEW SANU K

US89 patents

⚠️ This page may combine multiple inventors who share the name “MATHEW SANU K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHEW SANU K

INTEL CORP

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Instructions and logic to perform floating-point and integer operations for machine learning

Methods and apparatus to parallelize data decompression

Variable precision floating point multiply-add circuit

Soft dark bit masking with integrated load modulation and burn-in induced destabilization for physically unclonable function keys

Full-swing source-follower leakage tolerant dynamic logic

Fast bit-parallel Viterbi decoder add-compare-select circuit

Sparse tree adder circuit

Double affine mapped S-box hardware accelerator

Methods and apparatus to parallelize data decompression

Method and apparatus for decompression acceleration in multi-cycle decoder based platforms

Physically unclonable circuit having a programmable input for improved dark bit mask accuracy

Stable probing-resilient physically unclonable function (PUF) circuit

Secure key storage

Integrated circuits having accessible and inaccessible physically unclonable functions

Apparatus and method for an address generation circuit

High-performance adder

Robust shadow bitline circuit technique for high-performance register files

Variable virtual ground domino logic with leakage control

Instructions and logic to perform floating point and integer operations for machine learning

Method and apparatus to provide memory based physically unclonable functions

Adaptive speculative decoding

Unified hardware accelerator for symmetric-key ciphers

Methods and apparatus to parallelize data decompression

Efficient length limiting of compression codes

Random number generator that includes physically unclonable circuits

Multi-stage non-linearly cascaded physically unclonable function circuit

System, apparatus and method for providing a unique identifier in a fuseless semiconductor device

Methods and apparatus to parallelize data decompression

Energy-efficient bitcoin mining hardware accelerators

Hardware apparatuses and methods for data decompression

Optimized SHA-256 datapath for energy-efficient high-performance Bitcoin mining

Hybrid SM3 and SHA acceleration processors

Non-linear physically unclonable function (PUF) circuit with machine-learning attack resistance

Hardware accelerator for cryptographic hash operations

Random number generator

Composite field scaled affine transforms-based hardware accelerator

Efficient huffman decoder improvements

Systems, apparatuses, and methods for K nearest neighbor search

Instruction and logic for accelerated compressed data decoding

Stable probing-resilient physically unclonable function (PUF) circuit

Grouping of physically unclonable functions

MATHEW SANU K

Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location

On-the-fly key generation for encryption and decryption

LI JIANGTAO

Secure key storage using physically unclonable functions

SRINIVASAN SURESH

Split path multiply accumulate unit

SATPATHY SUDHIR K

Hybrid CAM assisted deflate decompression accelerator