Inventor

YAP KIRK S

US97 patents

⚠️ This page may combine multiple inventors who share the name “YAP KIRK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAP KIRK S

INTEL CORP

Technologies for performing speculative decompression

Technologies for performing speculative decompression

Technologies for flexibly compressing and decompressing data

Technologies for performing low-latency decompression with tree caching

Technologies for high-performance single-stream LZ77 compression

Method and apparatus for accelerating canonical huffman encoding

Techniques for data compression verification

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Instruction and logic to provide SIMD secure hashing round slice functionality

Encryption interface

Instruction and logic to provide SIMD secure hashing round slice functionality

SM3 hash function message expansion processors, methods, systems, and instructions

Double affine mapped S-box hardware accelerator

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Techniques for parallel data compression

Instructions and logic to provide SIMD SM3 cryptographic hashing functionality

SMS4 acceleration processors, methods, systems, and instructions

Instructions processors, methods, and systems to process secure hash algorithms

Instructions processors, methods, and systems to process secure hash algorithms

Method and apparatus for generic multi-stage nested hash processing

Method and apparatus to process SHA-2 secure hashing algorithm

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Method and apparatus to process SHA-2 secure hashing algorithm

Systems, methods, and apparatuses for decompression using hardware and software

Instructions processors, methods, and systems to process secure hash algorithms

Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match

Method and apparatus to process SHA-2 secure hashing algorithm

Method and apparatus to process SHA-2 secure hashing algorithm

Instruction and logic to provide SIMD secure hashing round slice functionality

Apparatus for hardware implementation of heterogeneous decompression processing

Method and apparatus for efficiently executing hash operations

Using a memory address to form a tweak key to use to encrypt and decrypt data

Instruction for accelerating SNOW 3G wireless security algorithm

Efficient data compression for solid-state memory

Instructions processors, methods, and systems to process secure hash algorithms

Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box

Delayed link compression scheme

In-field system test security

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

System, apparatus and method for providing protection against silent data corruption in a link

Instructions and logic to provide SIMD SM4 cryptographic block cipher

Instructions processors, methods, and systems to process secure hash algorithms

GOPAL VINODH

Matrix multiply accumulate instruction

SIMD integer multiply-accumulate instruction for multi-precision arithmetic

Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Method and apparatus for advanced encryption standard (AES) block cipher

WOLRICH GILBERT M

Instruction set for message scheduling of SHA256 algorithm

Instructions to perform Groestl hashing

YAP KIRK S

Method and apparatus to process KECCAK secure hashing algorithm

Method and apparatus to process SHA-2 secure hashing algorithm