Inventor

STEISS DONALD E

US31 patents

⚠️ This page may combine multiple inventors who share the name “STEISS DONALD E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEISS DONALD E

TEXAS INSTRUMENTS INC

Multi-stream complex instruction set microprocessor

Microprocessor with non-aligned memory access

Secure computing device including operating system stored in non-relocatable page of memory

Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return

Pipelined microprocessor with efficient self-modifying code detection and handling

Selectively powering X Y organized memory banks

Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes

Single event upset tolerant microprocessor architecture

Shared floating-point unit in a single chip multiprocessor

Microprocessor arithmetic logic unit using multiple number representations

Device for having processors each having interface for transferring delivery units specifying direction and distance and operable to emulate plurality of field programmable gate arrays

Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register

System for verifying leaf-cell circuit properties

Microprocessor with conditional cross path stall to minimize CPU cycle time length

Power-off state storage apparatus and method

Circuits, systems, and methods for external evaluation of microprocessor built-in self-test

Flip flop with reduced leakage current

Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory

System and method for processing data in an integrated circuit environment

Real time input/output address translation for virtualized systems

High speed numerical processor for performing a plurality of numeric functions

Real time input/output address translation for virtualized systems

Sub-pipelined and pipelined execution in a VLIW

Method and circuit for redefining bits in a control register

CISCO TECH INC

Thread-aware instruction fetching in a multithreaded embedded processor

Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor

Descriptor transfer logic

Reduced stack usage in a multithreaded processor

STEISS DONALD E

Translation look-aside buffer with variable page sizes

System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions

Thread interleaving in a multithreaded embedded processor