Inventor
WISTORT REID A
US20 patents
⚠️ This page may combine multiple inventors who share the name “WISTORT REID A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS6373738B1Apr 16, 2002
Low power CAM match line circuit
IBM143 citations97
US7924588B2Apr 12, 2011
Content addressable memory with concurrent two-dimensional search capability in both row and column directions
IBM23 citations92
US6201750B1Mar 13, 2001
Scannable fuse latches
IBM28 citations92
US6697277B2Feb 24, 2004
Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances
IBM22 citations90
US6618279B2Sep 9, 2003
Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)
IBM19 citations90
US6998897B2Feb 14, 2006
System and method for implementing a micro-stepping delay chain for a delay locked loop
IBM13 citations84
US7515449B2Apr 7, 2009
CAM asynchronous search-line switching
IBM10 citations83
US7688611B2Mar 30, 2010
CAM asynchronous search-line switching
IBM14 citations79
US7049873B2May 23, 2006
System and method for implementing a micro-stepping delay chain for a delay locked loop
IBM10 citations74
US5638315AJun 10, 1997
Content addressable memory for a data processing system
IBM15 citations74
US6791855B2Sep 14, 2004
Redundant array architecture for word replacement in CAM
IBM11 citations73
US6728123B2Apr 27, 2004
Redundant array architecture for word replacement in CAM
IBM8 citations73
US6396336B2May 28, 2002
Sleep mode VDD detune for power reduction
IBM8 citations73
US7117400B2Oct 3, 2006
Memory device with data line steering and bitline redundancy
IBM5 citations62
US6333671B1Dec 25, 2001
Sleep mode VDD detune for power reduction
IBM3 citations62
US6356981B1Mar 12, 2002
Method and apparatus for preserving data coherency in a double data rate SRAM
IBM0 citations41
ARSOVSKI IGOR
4 patentsUS8233302B2Jul 31, 2012
Content addressable memory with concurrent read and search/compare operations at the same memory cell
ARSOVSKI IGOR14 citations83
US9384835B2Jul 5, 2016
Content addressable memory early-predict late-correct single ended sensing
ARSOVSKI IGOR3 citations70
US8437201B2May 7, 2013
Word-line level shift circuit
ARSOVSKI IGOR2 citations59
US8218378B2Jul 10, 2012
Word-line level shift circuit
ARSOVSKI IGOR5 citations59