Inventor

YANG JEAN Y

US34 patents

⚠️ This page may combine multiple inventors who share the name “YANG JEAN Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG JEAN Y

ADVANCED MICRO DEVICES INC

Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types

Flash memory erase speed by fluorine implant or fluorination

Bitline hard mask spacer flow for memory cell scaling

Semiconductor memory with deuterated materials

Planar structure for non-volatile memory devices

Method of simultaneous formation of bitline isolation and periphery oxide

Disposable hard mask for memory bitline scaling

Simultaneous formation of charge storage and bitline to wordline isolation

Simultaneous formation of charge storage and bitline to wordline isolation

Flash memory with controlled wordline width

Structure and method for preventing UV radiation damage and increasing data retention in memory cells

Memory manufacturing process using bitline rapid thermal anneal

Memory wordline hard mask

Method of making memory wordline hard mask extension

Tightly spaced gate formation through damascene process

Flash memory cell with UV protective layer

Memory with disposable ARC for wordline formation

HSQ processing for reduced dielectric constant

Memory manufacturing process using disposable ARC for wordline formation

Hard mask process for memory device without bitline shorts

HSQ baking for reduced dielectric constant

Species implantation for minimizing interface defect density in flash memory devices

Species implantation for minimizing interface defect density in flash memory devices

FASL LLC

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device

Method of manufacturing a semiconductor memory with deuterated materials

SPANSION LLC

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process

UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing

Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control

Structure and method for preventing process-induced UV radiation damage in a memory cell

RAMSBEY MARK T

Memory manufacturing process with bitline isolation