Inventor

LEOBANDUNG EFFENDI

US497 patents

⚠️ This page may combine multiple inventors who share the name “LEOBANDUNG EFFENDI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEOBANDUNG EFFENDI

IBM

MOSFET with super-steep retrograded island

Strained silicon NMOS devices with embedded source/drain

Double planar gated SOI MOSFET structure

Process of making densely patterned silicon-on-insulator (SOI) region on a wafer

Integrated on chip detector and zero waveguide module structure for use in DNA sequencing

Stacked vertical devices

Back propagation gates and storage capacitor for neural networks

Integrated on chip detector and zero waveguide module structure for use in DNA sequencing

Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer

Integration of dual workfunction metal gate CMOS devices

Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures

Double planar gated SOI MOSFET structure

Process of fabricating planar and densely patterned silicon-on-insulator structure

Unit cell with floating gate MOSFET for analog memory

Fabrication of nanowire vertical gate devices

Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and method of manufacturing the same

Integration of floating gate memory and logic device in replacement gate flow

Self-aligned replacement metal gate spacerless vertical field effect transistor

Vertical air gap subtractive etch back end metal

Monolithic integrated photonics with lateral bipolar and BiCMOS

Stacked semiconductor nanowires with tunnel spacers

Stacked semiconductor nanowires with tunnel spacers

Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture

Optoelectronics and CMOS integration on GOI substrate

Electrical and optical through-silicon-via (TSV)

Preventing FIN erosion and limiting Epi overburden in FinFET structures by composite hardmask

Preventing Fin erosion and limiting EPI overburden in FinFET structures by composite hardmask

finFET eDRAM strap connection structure

Method and structure for forming self-aligned, dual stress liner for CMOS devices

Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet

Fabricating a substantially self-aligned MOSFET

Densely patterned silicon-on-insulator (SOI) region on a wafer

Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET

Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall

Method to form dual channel group III-V and Si/Ge FINFET CMOS

Structure and method for manufacturing MOSFET with super-steep retrograded island

MOSFET device with in-situ doped, raised source and drain structures

Method of integrating substrate contact on SOI wafers with STI process

Process of making buried capacitor for silicon-on-insulator structure

Buried capacitor for silicon-on-insulator structure

Resistive processing units with complementary metal-oxide-semiconductor non-volatile analog memory

Self-contained liquid cooled semiconductor packaging

Semiconductor circuit including nanosheets and fins on the same wafer

BASKER VEERARAGHAVAN S

SOI FinFET with recessed merged Fins and liner for enhanced stress coupling

Finfet with reduced parasitic capacitance

Method for fabricating finFET with merged fins and vertical silicide

LEOBANDUNG EFFENDI

Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers

UNIV MINNESOTA

Single-electron floating-gate MOS memory

CHANG JOSEPHINE B

Raised isolation structure self-aligned to fin structures

ANGYAL MATTHEW S

Pedestal guard ring having continuous M1 metal barrier connected to crack stop